Simulation Results: edn/edn1

 
05/05/2026 15:30:24 DVSim: v1.34.0 sha: f7bfc3b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.75 %
  • code
  • 82.86 %
  • assert
  • 97.14 %
  • func
  • 80.25 %
  • line
  • 98.18 %
  • branch
  • 93.51 %
  • cond
  • 89.38 %
  • toggle
  • 86.65 %
  • FSM
  • 46.59 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.960s 21.377us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.730s 90.186us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.780s 16.180us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.170s 66.725us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 0.970s 89.490us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.830s 62.257us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.780s 16.180us 1 1 100.00
edn_csr_aliasing 0.970s 89.490us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.020s 80.471us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.020s 80.471us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.020s 80.471us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.940s 28.300us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.970s 28.119us 1 1 100.00
errs 1 1 100.00
edn_err 0.910s 24.378us 1 1 100.00
disable 2 2 100.00
edn_disable 0.720s 76.992us 1 1 100.00
edn_disable_auto_req_mode 0.860s 83.801us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.130s 139.012us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.740s 13.986us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.780s 70.012us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.880s 261.559us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.880s 261.559us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.730s 90.186us 1 1 100.00
edn_csr_rw 0.780s 16.180us 1 1 100.00
edn_csr_aliasing 0.970s 89.490us 1 1 100.00
edn_same_csr_outstanding 0.960s 56.773us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.730s 90.186us 1 1 100.00
edn_csr_rw 0.780s 16.180us 1 1 100.00
edn_csr_aliasing 0.970s 89.490us 1 1 100.00
edn_same_csr_outstanding 0.960s 56.773us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.560s 640.682us 1 1 100.00
edn_tl_intg_err 1.600s 175.445us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.820s 25.240us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.970s 28.119us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.560s 640.682us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.560s 640.682us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.560s 640.682us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.560s 640.682us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.970s 28.119us 1 1 100.00
edn_sec_cm 3.560s 640.682us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.970s 28.119us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.600s 175.445us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 46.950s 16299.514us 1 1 100.00