Simulation Results: flash_ctrl

 
05/05/2026 15:30:24 DVSim: v1.34.0 sha: f7bfc3b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.97 %
  • code
  • 93.94 %
  • assert
  • 89.42 %
  • func
  • 95.54 %
  • line
  • 95.97 %
  • branch
  • 97.06 %
  • cond
  • 94.03 %
  • toggle
  • 98.31 %
  • FSM
  • 84.35 %
Validation stages
V1
100.00%
V2
98.28%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 46.890s 43.542us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 8.410s 75.991us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 18.030s 27.226us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 10.490s 206.711us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 56.620s 9506.875us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 20.590s 647.891us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 7.720s 49.773us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 10.490s 206.711us 1 1 100.00
flash_ctrl_csr_aliasing 20.590s 647.891us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 5.300s 71.137us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 5.480s 20.274us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 8.750s 37.962us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 14.170s 26.693us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1092.720s 85399.108us 1 1 100.00
flash_ctrl_hw_rma_reset 529.940s 40129.407us 1 1 100.00
flash_ctrl_lcmgr_intg 5.320s 77.907us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1473.540s 532909.952us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 199.390s 2092.505us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 5.410s 23.421us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 1696.370s 93116.261us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 33.830s 151.921us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 11.880s 79.392us 1 1 100.00
flash_ctrl_rw_evict_all_en 10.940s 113.333us 1 1 100.00
flash_ctrl_re_evict 14.910s 71.900us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 17.660s 86.060us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 17.660s 86.060us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 202.740s 14999.768us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 13.210s 1166.834us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 59.440s 243.741us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 341.030s 7828.754us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 273.300s 2510.967us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 599.600s 1399.718us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 5.340s 37.422us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 100.270s 1308.387us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 8.540s 36.083us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 5.420s 27.456us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 487.290s 472.719us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 85.920s 3386.095us 1 1 100.00
flash_ctrl_otp_reset 38.190s 73.040us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1092.720s 85399.108us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 131.210s 3226.626us 1 1 100.00
flash_ctrl_intr_wr 43.870s 4525.368us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 157.530s 12773.382us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 126.280s 48992.390us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 42.070s 3461.340us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 32.470s 866.460us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 9.300s 25.323us 1 1 100.00
flash_ctrl_ro_derr 92.340s 681.105us 1 1 100.00
flash_ctrl_rw_derr 104.440s 2619.213us 1 1 100.00
flash_ctrl_derr_detect 118.560s 1383.850us 1 1 100.00
flash_ctrl_integrity 384.040s 31267.181us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 8.390s 36.344us 1 1 100.00
flash_ctrl_ro_serr 77.310s 648.564us 1 1 100.00
flash_ctrl_rw_serr 117.890s 1706.253us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 40.040s 2421.199us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 75.630s 11597.083us 1 1 100.00
scramble 4 5 80.00
flash_ctrl_wo 1871.450s 200000.000us 0 1 0.00
flash_ctrl_write_word_sweep 6.290s 373.985us 1 1 100.00
flash_ctrl_read_word_sweep 5.530s 25.690us 1 1 100.00
flash_ctrl_ro 74.230s 1725.703us 1 1 100.00
flash_ctrl_rw 394.100s 17539.765us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 22.460s 331.944us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 977.680s 497617.131us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 35.500s 10049.405us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 5.450s 45.977us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 5.390s 43.276us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 9.990s 217.754us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 9.990s 217.754us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 18.030s 27.226us 1 1 100.00
flash_ctrl_csr_rw 10.490s 206.711us 1 1 100.00
flash_ctrl_csr_aliasing 20.590s 647.891us 1 1 100.00
flash_ctrl_same_csr_outstanding 7.790s 81.925us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 18.030s 27.226us 1 1 100.00
flash_ctrl_csr_rw 10.490s 206.711us 1 1 100.00
flash_ctrl_csr_aliasing 20.590s 647.891us 1 1 100.00
flash_ctrl_same_csr_outstanding 7.790s 81.925us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 17.060s 104.259us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 17.060s 104.259us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 17.060s 104.259us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 17.060s 104.259us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 23.750s 59.252us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_sec_cm 1453.170s 1480.458us 1 1 100.00
flash_ctrl_tl_intg_err 170.280s 193.840us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 170.280s 193.840us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 170.280s 193.840us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 12.260s 63.694us 1 1 100.00
flash_ctrl_wr_intg 5.890s 159.685us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 46.890s 43.542us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 38.190s 73.040us 1 1 100.00
flash_ctrl_disable 8.540s 36.083us 1 1 100.00
flash_ctrl_sec_info_access 30.330s 1082.260us 1 1 100.00
flash_ctrl_connect 5.420s 27.456us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 5.830s 22.919us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 10.490s 206.711us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 17.060s 104.259us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 10.490s 206.711us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 17.060s 104.259us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 10.490s 206.711us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 17.060s 104.259us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 8.540s 36.083us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 12.260s 63.694us 1 1 100.00
flash_ctrl_access_after_disable 5.540s 162.120us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 12.890s 27.842us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 8.540s 36.083us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 13.210s 1166.834us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 394.100s 17539.765us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 117.890s 1706.253us 1 1 100.00
flash_ctrl_rw_derr 104.440s 2619.213us 1 1 100.00
flash_ctrl_integrity 384.040s 31267.181us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1092.720s 85399.108us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1453.170s 1480.458us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1453.170s 1480.458us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1453.170s 1480.458us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1453.170s 1480.458us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 7.860s 847.292us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 5.930s 292.882us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 8.040s 236.233us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1453.170s 1480.458us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1453.170s 1480.458us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1453.170s 1480.458us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 18.080s 62.551us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 155.540s 777.365us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ns hit, indicating a probable testbench issue 1 test run
flash_ctrl_wo 85058228471519983758529613069437737971679316264717600925427173303052094321595 113
UVM_INFO @ 200000000.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---