Simulation Results: hmac

 
05/05/2026 15:30:24 DVSim: v1.34.0 sha: f7bfc3b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.28 %
  • code
  • 97.18 %
  • assert
  • 96.70 %
  • func
  • 43.96 %
  • line
  • 99.59 %
  • branch
  • 99.17 %
  • cond
  • 95.95 %
  • toggle
  • 100.00 %
  • FSM
  • 91.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 10.240s 303.811us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.850s 16.625us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.880s 105.952us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 4.190s 360.264us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 3.800s 432.230us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.000s 20.489us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.880s 105.952us 1 1 100.00
hmac_csr_aliasing 3.800s 432.230us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 32.440s 2621.723us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 54.990s 16697.398us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 151.160s 102319.780us 1 1 100.00
hmac_test_sha384_vectors 19.030s 241.438us 1 1 100.00
hmac_test_sha512_vectors 338.070s 9537.505us 1 1 100.00
hmac_test_hmac256_vectors 9.130s 2482.592us 1 1 100.00
hmac_test_hmac384_vectors 9.790s 603.107us 1 1 100.00
hmac_test_hmac512_vectors 12.270s 361.057us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 15.000s 1463.386us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 733.350s 22159.310us 1 1 100.00
error 1 1 100.00
hmac_error 36.780s 8234.361us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 71.180s 30254.360us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 10.240s 303.811us 1 1 100.00
hmac_long_msg 32.440s 2621.723us 1 1 100.00
hmac_back_pressure 54.990s 16697.398us 1 1 100.00
hmac_datapath_stress 733.350s 22159.310us 1 1 100.00
hmac_burst_wr 15.000s 1463.386us 1 1 100.00
hmac_stress_all 24.900s 2597.990us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 10.240s 303.811us 1 1 100.00
hmac_long_msg 32.440s 2621.723us 1 1 100.00
hmac_back_pressure 54.990s 16697.398us 1 1 100.00
hmac_datapath_stress 733.350s 22159.310us 1 1 100.00
hmac_wipe_secret 71.180s 30254.360us 1 1 100.00
hmac_test_sha256_vectors 151.160s 102319.780us 1 1 100.00
hmac_test_sha384_vectors 19.030s 241.438us 1 1 100.00
hmac_test_sha512_vectors 338.070s 9537.505us 1 1 100.00
hmac_test_hmac256_vectors 9.130s 2482.592us 1 1 100.00
hmac_test_hmac384_vectors 9.790s 603.107us 1 1 100.00
hmac_test_hmac512_vectors 12.270s 361.057us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 10.240s 303.811us 1 1 100.00
hmac_long_msg 32.440s 2621.723us 1 1 100.00
hmac_back_pressure 54.990s 16697.398us 1 1 100.00
hmac_datapath_stress 733.350s 22159.310us 1 1 100.00
hmac_burst_wr 15.000s 1463.386us 1 1 100.00
hmac_error 36.780s 8234.361us 1 1 100.00
hmac_wipe_secret 71.180s 30254.360us 1 1 100.00
hmac_test_sha256_vectors 151.160s 102319.780us 1 1 100.00
hmac_test_sha384_vectors 19.030s 241.438us 1 1 100.00
hmac_test_sha512_vectors 338.070s 9537.505us 1 1 100.00
hmac_test_hmac256_vectors 9.130s 2482.592us 1 1 100.00
hmac_test_hmac384_vectors 9.790s 603.107us 1 1 100.00
hmac_test_hmac512_vectors 12.270s 361.057us 1 1 100.00
hmac_stress_all 24.900s 2597.990us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 24.900s 2597.990us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.580s 40.637us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.680s 60.786us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.390s 59.103us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.390s 59.103us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.850s 16.625us 1 1 100.00
hmac_csr_rw 0.880s 105.952us 1 1 100.00
hmac_csr_aliasing 3.800s 432.230us 1 1 100.00
hmac_same_csr_outstanding 0.960s 21.309us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.850s 16.625us 1 1 100.00
hmac_csr_rw 0.880s 105.952us 1 1 100.00
hmac_csr_aliasing 3.800s 432.230us 1 1 100.00
hmac_same_csr_outstanding 0.960s 21.309us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.860s 61.975us 1 1 100.00
hmac_tl_intg_err 2.470s 374.641us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.470s 374.641us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 10.240s 303.811us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 2.340s 130.782us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 32.550s 6527.416us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.060s 134.743us 1 1 100.00