Simulation Results

Simulation Results: i2c

05/05/2026 15:30:24 DVSim: v1.34.0 sha: f7bfc3b json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
86.88 %

code
81.47 %

assert
96.19 %

func
82.98 %

line
96.41 %

branch
92.33 %

cond
84.89 %

toggle
89.66 %

FSM
44.05 %

Validation stages

V1		100.00%
V2		87.80%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	19.860s	1891.413us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	7.580s	3492.352us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.690s	22.024us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.690s	26.304us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	3.260s	669.248us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.130s	66.020us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	0.750s	26.044us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.690s	26.304us	1	1	100.00
	i2c_csr_aliasing	1.130s	66.020us	1	1	100.00

36/41 passed

87.80 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	0.720s	33.068us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	112.310s	14076.697us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	445.830s	49311.494us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.640s	31.069us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	67.400s	5657.967us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	62.080s	3098.581us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	0.860s	97.389us	1	1	100.00
	i2c_host_fifo_fmt_empty	4.920s	1298.618us	1	1	100.00
	i2c_host_fifo_reset_rx	4.950s	2216.142us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	43.080s	10205.684us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	6.700s	2018.170us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	0.800s	87.024us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	2.030s	479.363us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	30.770s	36032.218us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	3.480s	1447.759us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	16.660s	847.736us	1	1	100.00
	i2c_target_intr_smoke	5.890s	1422.542us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	0.820s	287.693us	1	1	100.00
	i2c_target_fifo_reset_tx	1.010s	670.753us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	71.650s	61336.065us	1	1	100.00
	i2c_target_stress_rd	16.660s	847.736us	1	1	100.00
	i2c_target_intr_stress_wr	70.240s	13620.521us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	4.320s	1313.410us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	16.550s	2950.335us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	3.300s	3239.236us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	5.660s	10048.610us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	1.650s	1997.318us	1	1	100.00
	i2c_target_fifo_watermarks_tx	1.010s	123.034us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	445.830s	49311.494us	1	1	100.00
	i2c_host_perf_precise	10.980s	6201.237us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	6.700s	2018.170us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	3.070s	288.316us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	2.190s	968.985us	1	1	100.00
	i2c_target_nack_acqfull_addr	2.080s	2505.498us	1	1	100.00
	i2c_target_nack_txstretch	1.180s	262.954us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	14.320s	505.294us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	1.460s	509.853us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.660s	25.511us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.690s	38.189us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	1.430s	74.642us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	1.430s	74.642us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.690s	22.024us	1	1	100.00
	i2c_csr_rw	0.690s	26.304us	1	1	100.00
	i2c_csr_aliasing	1.130s	66.020us	1	1	100.00
	i2c_same_csr_outstanding	0.940s	20.154us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.690s	22.024us	1	1	100.00
	i2c_csr_rw	0.690s	26.304us	1	1	100.00
	i2c_csr_aliasing	1.130s	66.020us	1	1	100.00
	i2c_same_csr_outstanding	0.940s	20.154us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	1.160s	80.037us	1	1	100.00
	i2c_sec_cm	0.890s	77.178us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.160s	80.037us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	10.110s	1637.546us	1
target_error_intr				1
	i2c_target_unexp_stop	0.840s	1350.207us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	3.510s	394.408us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				3 test runs
	i2c_host_error_intr	111038048135677505941735447818717772339613141552791809101849827523495378788622	93	UVM_INFO @ 33067883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_stress_all	98772077805360410100269320934090197291266371052903215337258593020981881532710	127	UVM_INFO @ 14076697188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	23854013269248404968640193867409251927485017487992824691250276881390660907701	93	UVM_INFO @ 394408195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	60224612422448580695153835046156749601931308692889887989012088842417662392982	89	UVM_INFO @ 479363445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [] vs [*])				1 test run
	i2c_target_unexp_stop	41814529934368582733116995275459959103033629594274189958602671505503416546605	83	UVM_INFO @ 1350207433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!				1 test run
	i2c_target_hrst	99585580007085094588633534085725008475016889137665142256650793901474858448948	84	UVM_INFO @ 10048610059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				1 test run
	i2c_host_stress_all_with_rand_reset	114502065065461626676512795040873829363364671199132917474243291192738780100807	102	UVM_INFO @ 1637546497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead				1 test run
	i2c_host_mode_toggle	39380115186425976515091425730781166460579028606192564002272742534728822557408	92	--> EXP: --------------------------------------------------- Name Type Size Value ---------------------------------------------------