Simulation Results: lc_ctrl/volatile_unlock_disabled

 
05/05/2026 15:30:24 DVSim: v1.34.0 sha: f7bfc3b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.67 %
  • code
  • 83.42 %
  • assert
  • 94.13 %
  • func
  • 91.46 %
  • line
  • 97.12 %
  • branch
  • 93.82 %
  • cond
  • 79.59 %
  • toggle
  • 85.80 %
  • FSM
  • 60.75 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.200s 17.706us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.200s 20.192us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.750s 108.594us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.550s 82.315us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 0.980s 26.127us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.370s 25.815us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.750s 108.594us 1 1 100.00
lc_ctrl_csr_aliasing 0.980s 26.127us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 6.200s 186.449us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 12.670s 1208.914us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.010s 51.921us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.380s 45.609us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 8.720s 3284.602us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 7.450s 2488.552us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 8.720s 3284.602us 1 1 100.00
lc_ctrl_prog_failure 1.380s 45.609us 1 1 100.00
lc_ctrl_errors 7.450s 2488.552us 1 1 100.00
lc_ctrl_security_escalation 6.950s 932.315us 1 1 100.00
lc_ctrl_jtag_state_failure 21.610s 1316.880us 1 1 100.00
lc_ctrl_jtag_prog_failure 1.810s 65.851us 1 1 100.00
lc_ctrl_jtag_errors 17.850s 829.459us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 2.380s 161.791us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.960s 473.508us 1 1 100.00
lc_ctrl_jtag_prog_failure 1.810s 65.851us 1 1 100.00
lc_ctrl_jtag_errors 17.850s 829.459us 1 1 100.00
lc_ctrl_jtag_access 3.300s 236.795us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 26.470s 2717.908us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.950s 732.452us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.490s 322.390us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 4.970s 1207.430us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 6.300s 325.166us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.120s 81.707us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.300s 593.346us 1 1 100.00
lc_ctrl_jtag_alert_test 1.530s 77.309us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 5.110s 3566.658us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.850s 45.916us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 13.270s 782.964us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.270s 166.243us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.790s 56.852us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.790s 56.852us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.200s 20.192us 1 1 100.00
lc_ctrl_csr_rw 0.750s 108.594us 1 1 100.00
lc_ctrl_csr_aliasing 0.980s 26.127us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.290s 17.701us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.200s 20.192us 1 1 100.00
lc_ctrl_csr_rw 0.750s 108.594us 1 1 100.00
lc_ctrl_csr_aliasing 0.980s 26.127us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.290s 17.701us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.050s 219.324us 1 1 100.00
lc_ctrl_tl_intg_err 1.610s 89.839us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.610s 89.839us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 12.670s 1208.914us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 8.720s 3284.602us 1 1 100.00
lc_ctrl_sec_cm 6.050s 219.324us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 8.720s 3284.602us 1 1 100.00
lc_ctrl_sec_cm 6.050s 219.324us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.720s 3284.602us 1 1 100.00
lc_ctrl_sec_cm 6.050s 219.324us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.720s 3284.602us 1 1 100.00
lc_ctrl_sec_cm 6.050s 219.324us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 8.720s 3284.602us 1 1 100.00
lc_ctrl_sec_cm 6.050s 219.324us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.720s 3284.602us 1 1 100.00
lc_ctrl_sec_cm 6.050s 219.324us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.720s 3284.602us 1 1 100.00
lc_ctrl_sec_cm 6.050s 219.324us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 8.720s 3284.602us 1 1 100.00
lc_ctrl_sec_cm 6.050s 219.324us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.950s 932.315us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 6.200s 186.449us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.960s 473.508us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.120s 298.096us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.120s 298.096us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.220s 384.800us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.900s 2284.199us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.900s 2284.199us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 35.150s 1685.867us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 1054473987563004427358186001729458672524556419128569735467706374529427791205 1518
UVM_INFO @ 1685866832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---