Simulation Results: lc_ctrl/volatile_unlock_enabled

 
05/05/2026 15:30:24 DVSim: v1.34.0 sha: f7bfc3b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.71 %
  • code
  • 84.42 %
  • assert
  • 94.13 %
  • func
  • 93.59 %
  • line
  • 97.15 %
  • branch
  • 93.62 %
  • cond
  • 78.94 %
  • toggle
  • 88.86 %
  • FSM
  • 63.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.830s 94.701us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.760s 20.028us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.710s 25.276us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.170s 90.216us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.230s 24.140us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.940s 19.052us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.710s 25.276us 1 1 100.00
lc_ctrl_csr_aliasing 1.230s 24.140us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.450s 64.621us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 8.710s 325.974us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.810s 36.695us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.380s 19.684us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.830s 2710.581us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.660s 7430.287us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 7.830s 2710.581us 1 1 100.00
lc_ctrl_prog_failure 1.380s 19.684us 1 1 100.00
lc_ctrl_errors 5.660s 7430.287us 1 1 100.00
lc_ctrl_security_escalation 7.140s 781.821us 1 1 100.00
lc_ctrl_jtag_state_failure 21.180s 10331.949us 1 1 100.00
lc_ctrl_jtag_prog_failure 7.270s 1337.728us 1 1 100.00
lc_ctrl_jtag_errors 37.910s 9006.700us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 4.390s 4378.161us 1 1 100.00
lc_ctrl_jtag_state_post_trans 16.280s 1250.639us 1 1 100.00
lc_ctrl_jtag_prog_failure 7.270s 1337.728us 1 1 100.00
lc_ctrl_jtag_errors 37.910s 9006.700us 1 1 100.00
lc_ctrl_jtag_access 3.800s 164.574us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 24.140s 1282.221us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.750s 292.117us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.560s 402.559us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 3.050s 340.203us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.950s 704.053us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.060s 29.500us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.620s 103.284us 1 1 100.00
lc_ctrl_jtag_alert_test 1.060s 42.533us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 9.730s 16492.168us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.160s 13.364us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 107.910s 38541.783us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.890s 38.358us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.250s 149.235us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.250s 149.235us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.760s 20.028us 1 1 100.00
lc_ctrl_csr_rw 0.710s 25.276us 1 1 100.00
lc_ctrl_csr_aliasing 1.230s 24.140us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.490s 22.942us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.760s 20.028us 1 1 100.00
lc_ctrl_csr_rw 0.710s 25.276us 1 1 100.00
lc_ctrl_csr_aliasing 1.230s 24.140us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.490s 22.942us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.880s 931.694us 1 1 100.00
lc_ctrl_tl_intg_err 2.320s 303.913us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.320s 303.913us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 8.710s 325.974us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.830s 2710.581us 1 1 100.00
lc_ctrl_sec_cm 6.880s 931.694us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.830s 2710.581us 1 1 100.00
lc_ctrl_sec_cm 6.880s 931.694us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.830s 2710.581us 1 1 100.00
lc_ctrl_sec_cm 6.880s 931.694us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.830s 2710.581us 1 1 100.00
lc_ctrl_sec_cm 6.880s 931.694us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.830s 2710.581us 1 1 100.00
lc_ctrl_sec_cm 6.880s 931.694us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.830s 2710.581us 1 1 100.00
lc_ctrl_sec_cm 6.880s 931.694us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.830s 2710.581us 1 1 100.00
lc_ctrl_sec_cm 6.880s 931.694us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.830s 2710.581us 1 1 100.00
lc_ctrl_sec_cm 6.880s 931.694us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 7.140s 781.821us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.450s 64.621us 1 1 100.00
lc_ctrl_jtag_state_post_trans 16.280s 1250.639us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.460s 316.996us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.460s 316.996us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 10.910s 1503.675us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 9.460s 992.121us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 9.460s 992.121us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 32.250s 1496.663us 1 1 100.00