Simulation Results: otbn

 
05/05/2026 15:30:24 DVSim: v1.34.0 sha: f7bfc3b json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.98 %
  • code
  • 95.34 %
  • assert
  • 89.57 %
  • func
  • 97.03 %
  • block
  • 99.40 %
  • line
  • 99.57 %
  • branch
  • 92.40 %
  • toggle
  • 91.95 %
  • FSM
  • 97.44 %
Validation stages
V1
100.00%
V2
92.86%
V2S
92.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 8.000s 68.434us 1 1 100.00
single_binary 1 1 100.00
otbn_single 5.000s 12.878us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 26.000s 28.287us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 25.000s 109.720us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 26.000s 56.063us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 25.000s 58.327us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 27.000s 163.473us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 25.000s 109.720us 1 1 100.00
otbn_csr_aliasing 25.000s 58.327us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 31.000s 533.096us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 34.000s 1025.423us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 26.000s 170.518us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 48.000s 256.774us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 42.000s 168.162us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 62.000s 1662.752us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 22.000s 22.891us 1 1 100.00
zero_state_err_urnd 0 1 0.00
otbn_zero_state_err_urnd 6.000s 38.215us 0 1 0.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 7.000s 40.989us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 26.000s 16.238us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 4.000s 40.071us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 6.000s 123.434us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 6.000s 123.434us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 26.000s 28.287us 1 1 100.00
otbn_csr_rw 25.000s 109.720us 1 1 100.00
otbn_csr_aliasing 25.000s 58.327us 1 1 100.00
otbn_same_csr_outstanding 5.000s 18.556us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 26.000s 28.287us 1 1 100.00
otbn_csr_rw 25.000s 109.720us 1 1 100.00
otbn_csr_aliasing 25.000s 58.327us 1 1 100.00
otbn_same_csr_outstanding 5.000s 18.556us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 7.000s 28.314us 1 1 100.00
otbn_dmem_err 24.000s 16.760us 1 1 100.00
internal_integrity 3 4 75.00
otbn_alu_bignum_mod_err 37.000s 62.204us 1 1 100.00
otbn_controller_ispr_rdata_err 30.000s 63.556us 1 1 100.00
otbn_mac_bignum_acc_err 15.000s 40.777us 1 1 100.00
otbn_urnd_err 4.000s 3.074us 0 1 0.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 13.000s 27.649us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 5.000s 44.568us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 4.000s 30.183us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 92.000s 519.825us 1 1 100.00
otbn_tl_intg_err 9.000s 227.885us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 40.000s 208.860us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 92.000s 519.825us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 92.000s 519.825us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 8.000s 68.434us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 24.000s 16.760us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 7.000s 28.314us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 9.000s 227.885us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 22.000s 22.891us 1 1 100.00
sec_cm_controller_fsm_local_esc 4 5 80.00
otbn_imem_err 7.000s 28.314us 1 1 100.00
otbn_dmem_err 24.000s 16.760us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 38.215us 0 1 0.00
otbn_illegal_mem_acc 13.000s 27.649us 1 1 100.00
otbn_sec_cm 92.000s 519.825us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 92.000s 519.825us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 5.000s 12.878us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 7.000s 28.314us 1 1 100.00
otbn_dmem_err 24.000s 16.760us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 38.215us 0 1 0.00
otbn_illegal_mem_acc 13.000s 27.649us 1 1 100.00
otbn_sec_cm 92.000s 519.825us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 92.000s 519.825us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 22.000s 22.891us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 7.000s 28.314us 1 1 100.00
otbn_dmem_err 24.000s 16.760us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 38.215us 0 1 0.00
otbn_illegal_mem_acc 13.000s 27.649us 1 1 100.00
otbn_sec_cm 92.000s 519.825us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 92.000s 519.825us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 5.000s 12.878us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 27.000s 21.185us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 6.000s 25.037us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 30.000s 227.926us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 30.000s 227.926us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 8.000s 71.240us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 92.000s 519.825us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 92.000s 519.825us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 7.000s 53.684us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 92.000s 519.825us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 92.000s 519.825us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 6.000s 14.209us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 6.000s 14.209us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 5.000s 29.013us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 5.000s 12.878us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 5.000s 12.878us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 5.000s 12.878us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 42.000s 168.162us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 5.000s 12.878us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 5.000s 12.878us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 8.000s 188.029us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 5.000s 12.878us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 92.000s 519.825us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
otbn_stress_all_with_rand_reset 130.000s 2576.391us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 8.000s 22.389us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.u_otbn_core.u_otbn_rnd.u_xoshiro256pp.xoshiro_q cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) 1 test run
otbn_zero_state_err_urnd 70891363823181575699266666497241676496837391388746840346899382925211345050404 108
UVM_INFO @ 38214586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.edn_urnd_ack cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) 1 test run
otbn_urnd_err 74821602696500997525674301119595310375505397866793739074386111996932745516153 105
UVM_INFO @ 3073994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---