Simulation Results: otp_ctrl

 
05/05/2026 15:30:24 DVSim: v1.34.0 sha: f7bfc3b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.17 %
  • code
  • 79.36 %
  • assert
  • 94.18 %
  • func
  • 75.96 %
  • line
  • 88.78 %
  • branch
  • 83.40 %
  • cond
  • 90.27 %
  • toggle
  • 89.22 %
  • FSM
  • 45.14 %
Validation stages
V1
100.00%
V2
95.00%
V2S
88.89%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 2.020s 56.419us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 4.780s 407.522us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 1.700s 179.236us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 2.010s 624.492us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 4.140s 265.744us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 4.420s 361.992us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 3.520s 1698.813us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 2.010s 624.492us 1 1 100.00
otp_ctrl_csr_aliasing 4.420s 361.992us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.220s 74.782us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.160s 47.216us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 12.700s 613.895us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 3.610s 411.621us 1 1 100.00
partition_check 2 2 100.00
otp_ctrl_background_chks 12.670s 1869.808us 1 1 100.00
otp_ctrl_check_fail 8.830s 8763.638us 1 1 100.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 4.940s 1922.555us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 10.400s 650.519us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 23.000s 1619.407us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 4.760s 621.265us 1 1 100.00
otp_ctrl_parallel_lc_esc 7.560s 732.848us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 8.340s 463.355us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 6.240s 682.247us 0 1 0.00
test_access 1 1 100.00
otp_ctrl_test_access 10.680s 2340.430us 1 1 100.00
stress_all 1 1 100.00
otp_ctrl_stress_all 160.040s 31507.310us 1 1 100.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.360s 579.096us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 2.340s 622.070us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 2.850s 367.872us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 2.850s 367.872us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.700s 179.236us 1 1 100.00
otp_ctrl_csr_rw 2.010s 624.492us 1 1 100.00
otp_ctrl_csr_aliasing 4.420s 361.992us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.010s 183.654us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.700s 179.236us 1 1 100.00
otp_ctrl_csr_rw 2.010s 624.492us 1 1 100.00
otp_ctrl_csr_aliasing 4.420s 361.992us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.010s 183.654us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 112.320s 10784.761us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 112.320s 10784.761us 1 1 100.00
otp_ctrl_tl_intg_err 7.020s 652.017us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 112.320s 10784.761us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 112.320s 10784.761us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 7.020s 652.017us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 4.780s 407.522us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 4.780s 407.522us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 112.320s 10784.761us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 112.320s 10784.761us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 112.320s 10784.761us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 112.320s 10784.761us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 112.320s 10784.761us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 112.320s 10784.761us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 112.320s 10784.761us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 112.320s 10784.761us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 112.320s 10784.761us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 112.320s 10784.761us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 112.320s 10784.761us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 112.320s 10784.761us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 112.320s 10784.761us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 112.320s 10784.761us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 112.320s 10784.761us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 7.560s 732.848us 1 1 100.00
otp_ctrl_sec_cm 112.320s 10784.761us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.560s 732.848us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.560s 732.848us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 7.560s 732.848us 1 1 100.00
otp_ctrl_macro_errs 6.240s 682.247us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.560s 732.848us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 7.560s 732.848us 1 1 100.00
otp_ctrl_sec_cm 112.320s 10784.761us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 7.560s 732.848us 1 1 100.00
otp_ctrl_sec_cm 112.320s 10784.761us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.560s 732.848us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.560s 732.848us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 7.560s 732.848us 1 1 100.00
otp_ctrl_macro_errs 6.240s 682.247us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.560s 732.848us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 7.560s 732.848us 1 1 100.00
otp_ctrl_sec_cm 112.320s 10784.761us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 3.610s 411.621us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 1 1 100.00
otp_ctrl_check_fail 8.830s 8763.638us 1 1 100.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 10.400s 650.519us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 10.400s 650.519us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 10.400s 650.519us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 10.400s 650.519us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 10.400s 650.519us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 4.780s 407.522us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 10.400s 650.519us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 4.780s 407.522us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 112.320s 10784.761us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 4.940s 1922.555us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 4.780s 407.522us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 4.780s 407.522us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 6.240s 682.247us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 12.830s 7576.157us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 56.800s 12588.532us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 1 test run
otp_ctrl_macro_errs 13866505265448128369739349684027714343224587316880727596674569513079198240986 5983
UVM_INFO @ 682247236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 1 test run
otp_ctrl_stress_all_with_rand_reset 58719691025056569414839645236701350875157847516259518870390077571065415105859 9339
UVM_INFO @ 12588531778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---