Simulation Results: pwrmgr

 
05/05/2026 15:30:24 DVSim: v1.34.0 sha: f7bfc3b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.08 %
  • code
  • 94.43 %
  • assert
  • 96.08 %
  • func
  • 94.73 %
  • line
  • 98.92 %
  • branch
  • 95.42 %
  • cond
  • 93.78 %
  • toggle
  • 90.02 %
  • FSM
  • 94.00 %
Validation stages
V1
100.00%
V2
93.33%
V2S
80.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.730s 27.013us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.670s 106.540us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.640s 36.074us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 1.430s 83.787us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.910s 152.024us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.780s 77.294us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.640s 36.074us 1 1 100.00
pwrmgr_csr_aliasing 0.910s 152.024us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.720s 130.523us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.720s 130.523us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.860s 45.804us 1 1 100.00
pwrmgr_lowpower_invalid 0.730s 43.378us 1 1 100.00
reset 2 2 100.00
pwrmgr_reset 0.740s 46.309us 1 1 100.00
pwrmgr_reset_invalid 0.740s 143.550us 1 1 100.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.740s 46.309us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.890s 52.933us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.810s 116.545us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 1.050s 164.130us 1 1 100.00
stress_all 0 1 0.00
pwrmgr_stress_all 20.090s 11369.056us 0 1 0.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.600s 45.493us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.080s 81.530us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.080s 81.530us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.670s 106.540us 1 1 100.00
pwrmgr_csr_rw 0.640s 36.074us 1 1 100.00
pwrmgr_csr_aliasing 0.910s 152.024us 1 1 100.00
pwrmgr_same_csr_outstanding 0.720s 28.746us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.670s 106.540us 1 1 100.00
pwrmgr_csr_rw 0.640s 36.074us 1 1 100.00
pwrmgr_csr_aliasing 0.910s 152.024us 1 1 100.00
pwrmgr_same_csr_outstanding 0.720s 28.746us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
pwrmgr_tl_intg_err 0.590s 25.274us 0 1 0.00
pwrmgr_sec_cm 0.720s 49.845us 0 1 0.00
prim_count_check 0 1 0.00
pwrmgr_sec_cm 0.720s 49.845us 0 1 0.00
prim_fsm_check 0 1 0.00
pwrmgr_sec_cm 0.720s 49.845us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
pwrmgr_tl_intg_err 0.590s 25.274us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 2.100s 755.619us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 1 1 100.00
pwrmgr_wakeup_reset 0.890s 52.933us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.970s 70.627us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.590s 33.259us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 0 1 0.00
pwrmgr_sec_cm 0.720s 49.845us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
pwrmgr_sec_cm 0.720s 49.845us 0 1 0.00
sec_cm_fsm_terminal 0 1 0.00
pwrmgr_sec_cm 0.720s 49.845us 0 1 0.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.580s 90.564us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.580s 73.286us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.700s 71.755us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.640s 36.074us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.640s 36.074us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 0 1 0.00
pwrmgr_escalation_timeout 0.720s 98.826us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 2.570s 952.884us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [pwrmgr_common_vseq] expect alert:fatal_fault to fire 2 test runs
pwrmgr_tl_intg_err 108435910815610149912131137668266172191726996174319811693562005355614215392076 85
UVM_INFO @ 25274188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_sec_cm 66583448091184270443279033702531691211173756789094597705781202229517624560655 84
UVM_INFO @ 49844650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((!clk_en) || status)' 1 test run
pwrmgr_escalation_timeout 10427203692286072689067443213175819845582092926592446453300008055016679619663 79
UVM_ERROR @ 98825920 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 98825920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_vseq.sv:62) [pwrmgr_reset_vseq] wait timeout occurred! 1 test run
pwrmgr_stress_all 20370500100380437162197487350147903155127164466612059592986764233715694236979 750
UVM_INFO @ 11369055886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---