Simulation Results: rom_ctrl/32kb

 
05/05/2026 15:30:24 DVSim: v1.34.0 sha: f7bfc3b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.76 %
  • code
  • 99.26 %
  • assert
  • 96.66 %
  • func
  • 97.37 %
  • line
  • 99.59 %
  • branch
  • 99.27 %
  • cond
  • 98.22 %
  • toggle
  • 99.24 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 4.540s 138.373us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 4.180s 212.910us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 2.950s 1076.707us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.820s 299.462us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 4.150s 175.009us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.010s 214.008us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 2.950s 1076.707us 1 1 100.00
rom_ctrl_csr_aliasing 4.150s 175.009us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.680s 128.308us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.670s 206.394us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 3.910s 215.423us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 9.900s 603.045us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 8.910s 301.293us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 4.560s 180.878us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 6.590s 621.400us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 6.590s 621.400us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.180s 212.910us 1 1 100.00
rom_ctrl_csr_rw 2.950s 1076.707us 1 1 100.00
rom_ctrl_csr_aliasing 4.150s 175.009us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.450s 205.295us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.180s 212.910us 1 1 100.00
rom_ctrl_csr_rw 2.950s 1076.707us 1 1 100.00
rom_ctrl_csr_aliasing 4.150s 175.009us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.450s 205.295us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 78.920s 2939.911us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 13.330s 958.585us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 185.480s 777.328us 1 1 100.00
rom_ctrl_tl_intg_err 24.960s 251.839us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 185.480s 777.328us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 185.480s 777.328us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 78.920s 2939.911us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 78.920s 2939.911us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 78.920s 2939.911us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 78.920s 2939.911us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 78.920s 2939.911us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 185.480s 777.328us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 185.480s 777.328us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 4.540s 138.373us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 4.540s 138.373us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 4.540s 138.373us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 24.960s 251.839us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 78.920s 2939.911us 1 1 100.00
rom_ctrl_kmac_err_chk 8.910s 301.293us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 78.920s 2939.911us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 78.920s 2939.911us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 78.920s 2939.911us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 13.330s 958.585us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 185.480s 777.328us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 73.530s 11685.189us 1 1 100.00