Simulation Results: rom_ctrl/64kb

 
05/05/2026 15:30:24 DVSim: v1.34.0 sha: f7bfc3b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.80 %
  • code
  • 98.12 %
  • assert
  • 96.80 %
  • func
  • 95.47 %
  • line
  • 99.59 %
  • branch
  • 99.64 %
  • cond
  • 98.07 %
  • toggle
  • 99.97 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 7.300s 222.219us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 9.830s 736.740us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 7.200s 301.402us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 10.070s 4958.160us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 7.340s 293.721us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 5.970s 689.638us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 7.200s 301.402us 1 1 100.00
rom_ctrl_csr_aliasing 7.340s 293.721us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 5.680s 376.546us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 5.390s 2780.158us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 6.990s 217.671us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 27.040s 2443.506us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 14.470s 562.095us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 7.050s 1069.447us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 8.590s 727.667us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 8.590s 727.667us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 9.830s 736.740us 1 1 100.00
rom_ctrl_csr_rw 7.200s 301.402us 1 1 100.00
rom_ctrl_csr_aliasing 7.340s 293.721us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.350s 1112.463us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 9.830s 736.740us 1 1 100.00
rom_ctrl_csr_rw 7.200s 301.402us 1 1 100.00
rom_ctrl_csr_aliasing 7.340s 293.721us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.350s 1112.463us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 148.190s 17367.314us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 39.150s 1621.166us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 420.060s 2267.319us 1 1 100.00
rom_ctrl_tl_intg_err 94.530s 2724.737us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 420.060s 2267.319us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 420.060s 2267.319us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 148.190s 17367.314us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 148.190s 17367.314us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 148.190s 17367.314us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 148.190s 17367.314us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 148.190s 17367.314us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 420.060s 2267.319us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 420.060s 2267.319us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 7.300s 222.219us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 7.300s 222.219us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 7.300s 222.219us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 94.530s 2724.737us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 148.190s 17367.314us 1 1 100.00
rom_ctrl_kmac_err_chk 14.470s 562.095us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 148.190s 17367.314us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 148.190s 17367.314us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 148.190s 17367.314us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 39.150s 1621.166us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 420.060s 2267.319us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 61.300s 2250.960us 1 1 100.00