Simulation Results: rv_timer

 
05/05/2026 15:30:24 DVSim: v1.34.0 sha: f7bfc3b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.57 %
  • code
  • 100.00 %
  • assert
  • 96.82 %
  • func
  • 95.88 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.710s 203.160us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.560s 43.260us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.550s 32.436us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.770s 126.226us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.600s 48.251us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.830s 33.816us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.550s 32.436us 1 1 100.00
rv_timer_csr_aliasing 0.600s 48.251us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 0.730s 241.820us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 1.270s 938.231us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 181.340s 154438.567us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 181.340s 154438.567us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 3.820s 2677.385us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.630s 48.095us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.590s 13.530us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.470s 412.536us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.470s 412.536us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.560s 43.260us 1 1 100.00
rv_timer_csr_rw 0.550s 32.436us 1 1 100.00
rv_timer_csr_aliasing 0.600s 48.251us 1 1 100.00
rv_timer_same_csr_outstanding 0.630s 108.481us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.560s 43.260us 1 1 100.00
rv_timer_csr_rw 0.550s 32.436us 1 1 100.00
rv_timer_csr_aliasing 0.600s 48.251us 1 1 100.00
rv_timer_same_csr_outstanding 0.630s 108.481us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.800s 277.173us 1 1 100.00
rv_timer_tl_intg_err 1.170s 425.308us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.170s 425.308us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.630s 131.031us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.700s 174.988us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 31.370s 4815.303us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 2 test runs
rv_timer_min 55359176918733668633729110625631874415713004534422287760046150027398363403898 80
UVM_INFO @ 131030633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 50346938676365744715363926197234362401632083136600539853820827104919710622677 75
UVM_INFO @ 241819802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 85204986609750807359952054960718432681554721407193913686062763494955366069843 80
UVM_INFO @ 174988246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---