Simulation Results: spi_device/2p

 
05/05/2026 15:30:24 DVSim: v1.34.0 sha: f7bfc3b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.36 %
  • code
  • 94.12 %
  • assert
  • 94.62 %
  • func
  • 76.34 %
  • line
  • 99.10 %
  • branch
  • 98.33 %
  • cond
  • 96.07 %
  • toggle
  • 87.74 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 261.180s 166969.876us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 0.800s 76.625us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 2.070s 1747.752us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 22.640s 771.293us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 10.370s 609.916us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.010s 80.076us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 2.070s 1747.752us 1 1 100.00
spi_device_csr_aliasing 10.370s 609.916us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.630s 32.553us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.050s 136.493us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.710s 47.889us 1 1 100.00
mem_parity 1 1 100.00
spi_device_mem_parity 0.900s 37.772us 1 1 100.00
mem_cfg 1 1 100.00
spi_device_ram_cfg 0.650s 16.014us 1 1 100.00
tpm_read 1 1 100.00
spi_device_tpm_rw 0.670s 11.452us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 0.670s 11.452us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 0.670s 31.952us 1 1 100.00
spi_device_tpm_sts_read 0.960s 314.179us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 18.130s 10168.552us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 3.290s 1470.361us 1 1 100.00
spi_device_flash_all 50.900s 71571.329us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.130s 8807.790us 1 1 100.00
spi_device_flash_all 50.900s 71571.329us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.130s 8807.790us 1 1 100.00
spi_device_flash_all 50.900s 71571.329us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 50.900s 71571.329us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 2.390s 131.691us 1 1 100.00
spi_device_flash_all 50.900s 71571.329us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 2.390s 131.691us 1 1 100.00
spi_device_flash_all 50.900s 71571.329us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 2.390s 131.691us 1 1 100.00
spi_device_flash_all 50.900s 71571.329us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 2.390s 131.691us 1 1 100.00
spi_device_flash_all 50.900s 71571.329us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 2.390s 131.691us 1 1 100.00
spi_device_flash_all 50.900s 71571.329us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 2.560s 420.503us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 1.650s 92.501us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 1.650s 92.501us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 1.650s 92.501us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 8.710s 1361.778us 1 1 100.00
spi_device_read_buffer_direct 5.830s 6136.343us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 1.650s 92.501us 1 1 100.00
spi_device_flash_all 50.900s 71571.329us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 50.900s 71571.329us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 50.900s 71571.329us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 2.160s 173.667us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 2.160s 173.667us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 261.180s 166969.876us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 65.620s 20042.195us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 1.030s 237.146us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.670s 12.521us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.710s 27.315us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 1.740s 189.622us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 1.740s 189.622us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 0.800s 76.625us 1 1 100.00
spi_device_csr_rw 2.070s 1747.752us 1 1 100.00
spi_device_csr_aliasing 10.370s 609.916us 1 1 100.00
spi_device_same_csr_outstanding 3.060s 337.113us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 0.800s 76.625us 1 1 100.00
spi_device_csr_rw 2.070s 1747.752us 1 1 100.00
spi_device_csr_aliasing 10.370s 609.916us 1 1 100.00
spi_device_same_csr_outstanding 3.060s 337.113us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.050s 211.086us 1 1 100.00
spi_device_tl_intg_err 9.780s 791.561us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 9.780s 791.561us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 130.270s 54617.054us 1 1 100.00