Simulation Results: spi_host

 
05/05/2026 15:30:24 DVSim: v1.34.0 sha: f7bfc3b json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.61 %
  • code
  • 95.03 %
  • assert
  • 94.13 %
  • func
  • 88.66 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 8.000s 1154.401us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 21.519us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 2.000s 18.692us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 2.000s 1874.769us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 19.583us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 1.000s 91.070us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 2.000s 18.692us 1 1 100.00
spi_host_csr_aliasing 1.000s 19.583us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 2.000s 17.100us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 2.000s 30.916us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 1.000s 22.845us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 2.000s 36.483us 1 1 100.00
spi_host_error_cmd 1.000s 78.979us 1 1 100.00
spi_host_event 9.000s 2405.662us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 3.000s 123.684us 1 1 100.00
speed 1 1 100.00
spi_host_speed 3.000s 123.684us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 3.000s 123.684us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 3.000s 242.069us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 105.691us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 3.000s 123.684us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 3.000s 123.684us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 8.000s 1154.401us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 8.000s 1154.401us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 4.000s 758.273us 1 1 100.00
spien 1 1 100.00
spi_host_spien 6.000s 3074.660us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 40.000s 1458.459us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 3.000s 92.054us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 2.000s 36.483us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 2.000s 29.506us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 20.738us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 2.000s 199.617us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 2.000s 199.617us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 21.519us 1 1 100.00
spi_host_csr_rw 2.000s 18.692us 1 1 100.00
spi_host_csr_aliasing 1.000s 19.583us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 92.171us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 21.519us 1 1 100.00
spi_host_csr_rw 2.000s 18.692us 1 1 100.00
spi_host_csr_aliasing 1.000s 19.583us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 92.171us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 2.000s 329.217us 1 1 100.00
spi_host_sec_cm 1.000s 145.680us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 329.217us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_host_upper_range_clkdiv 62.000s 3577.526us 1 1 100.00