Simulation Results: sram_ctrl/main

 
05/05/2026 15:30:24 DVSim: v1.34.0 sha: f7bfc3b json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.15 %
  • code
  • 95.47 %
  • assert
  • 96.19 %
  • func
  • 93.80 %
  • block
  • 94.39 %
  • line
  • 94.88 %
  • branch
  • 90.92 %
  • toggle
  • 96.09 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 4.000s 868.522us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 14.838us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 19.492us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 27.067us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 20.896us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 369.170us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 19.492us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 20.896us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 143.000s 7881.685us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 67.000s 8210.265us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 20.000s 8238.200us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 90.000s 3822.405us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 121.000s 9911.183us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 8.000s 7026.276us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 12.000s 9808.024us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 20.000s 5822.467us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 2609.376us 1 1 100.00
sram_ctrl_partial_access_b2b 258.000s 40611.831us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 4.000s 693.694us 1 1 100.00
sram_ctrl_throughput_w_partial_write 4.000s 2665.272us 1 1 100.00
sram_ctrl_throughput_w_readback 4.000s 2794.611us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 12.000s 1454.508us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 3.000s 365.964us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 178.000s 80250.190us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 28.363us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 105.442us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 105.442us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 14.838us 1 1 100.00
sram_ctrl_csr_rw 1.000s 19.492us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 20.896us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 40.624us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 14.838us 1 1 100.00
sram_ctrl_csr_rw 1.000s 19.492us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 20.896us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 40.624us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 13.000s 15984.532us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 1815.673us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 1925.332us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 1815.673us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 1925.332us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 12.000s 1454.508us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 12.000s 1454.508us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 19.492us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 20.000s 5822.467us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 20.000s 5822.467us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 20.000s 5822.467us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 12.000s 9808.024us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 4.000s 2909.190us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 13.000s 15984.532us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 4.000s 3512.457us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 868.522us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 868.522us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 20.000s 5822.467us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 1815.673us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 12.000s 9808.024us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 1815.673us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 1815.673us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 4.000s 868.522us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 1815.673us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 10.000s 891.976us 1 1 100.00