Simulation Results: sysrst_ctrl

 
05/05/2026 15:30:24 DVSim: v1.34.0 sha: f7bfc3b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.65 %
  • code
  • 93.99 %
  • assert
  • 93.58 %
  • func
  • 60.39 %
  • line
  • 97.47 %
  • branch
  • 97.59 %
  • cond
  • 94.77 %
  • toggle
  • 100.00 %
  • FSM
  • 80.13 %
Validation stages
V1
100.00%
V2
94.44%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 4.360s 2109.162us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 4.720s 2450.226us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 2.850s 2421.755us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 4.620s 2300.739us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 3.920s 4044.917us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 2.410s 2053.572us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 37.080s 71119.903us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 2.050s 2670.197us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 1.980s 2118.055us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 2.410s 2053.572us 1 1 100.00
sysrst_ctrl_csr_aliasing 2.050s 2670.197us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 93.880s 53778.015us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 15.380s 28096.702us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 142.430s 157007.762us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 3.330s 3702.567us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 1.820s 2522.515us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 1.470s 2053.584us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 2.380s 4161.410us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 0.880s 2795.999us 1 1 100.00
ultra_low_power_test 0 1 0.00
sysrst_ctrl_ultra_low_pwr 2.850s 4159.218us 0 1 0.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 43.750s 40110.913us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 7.320s 13982.611us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 4.170s 2012.944us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 1.520s 2025.306us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 5.090s 2099.442us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 5.090s 2099.442us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 3.920s 4044.917us 1 1 100.00
sysrst_ctrl_csr_rw 2.410s 2053.572us 1 1 100.00
sysrst_ctrl_csr_aliasing 2.050s 2670.197us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 12.760s 5246.891us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 3.920s 4044.917us 1 1 100.00
sysrst_ctrl_csr_rw 2.410s 2053.572us 1 1 100.00
sysrst_ctrl_csr_aliasing 2.050s 2670.197us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 12.760s 5246.891us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 10.090s 42269.846us 1 1 100.00
sysrst_ctrl_tl_intg_err 78.350s 42391.377us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 78.350s 42391.377us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 54.550s 1115602.695us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error 1 test run
sysrst_ctrl_ultra_low_pwr 9606558397368861089942628649656142024334318458847640538694697321066806978664 665
UVM_ERROR @ 4159218084 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 4159218084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---