Simulation Results: uart

 
05/05/2026 15:30:24 DVSim: v1.34.0 sha: f7bfc3b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.63 %
  • code
  • 95.79 %
  • assert
  • 96.83 %
  • func
  • 58.28 %
  • line
  • 99.17 %
  • branch
  • 97.44 %
  • cond
  • 95.22 %
  • toggle
  • 91.32 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 19.350s 6287.411us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.560s 14.602us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.600s 25.925us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.130s 67.014us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.690s 96.412us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 1.000s 27.367us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.600s 25.925us 1 1 100.00
uart_csr_aliasing 0.690s 96.412us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 6.690s 83103.149us 1 1 100.00
parity 2 2 100.00
uart_smoke 19.350s 6287.411us 1 1 100.00
uart_tx_rx 6.690s 83103.149us 1 1 100.00
parity_error 2 2 100.00
uart_intr 13.860s 47007.400us 1 1 100.00
uart_rx_parity_err 54.580s 394846.433us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 6.690s 83103.149us 1 1 100.00
uart_intr 13.860s 47007.400us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 20.380s 75248.178us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 31.520s 26855.337us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 55.200s 214690.135us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 13.860s 47007.400us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 13.860s 47007.400us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 13.860s 47007.400us 1 1 100.00
perf 1 1 100.00
uart_perf 68.770s 23709.564us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 7.470s 6625.031us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 7.470s 6625.031us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 8.900s 35875.780us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 56.100s 49438.570us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 2.330s 676.254us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 8.340s 5070.331us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 202.020s 135538.729us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 107.590s 284211.052us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.540s 21.353us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.540s 12.659us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.300s 89.566us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.300s 89.566us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.560s 14.602us 1 1 100.00
uart_csr_rw 0.600s 25.925us 1 1 100.00
uart_csr_aliasing 0.690s 96.412us 1 1 100.00
uart_same_csr_outstanding 0.630s 172.140us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.560s 14.602us 1 1 100.00
uart_csr_rw 0.600s 25.925us 1 1 100.00
uart_csr_aliasing 0.690s 96.412us 1 1 100.00
uart_same_csr_outstanding 0.630s 172.140us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.700s 164.496us 1 1 100.00
uart_tl_intg_err 0.840s 48.724us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 0.840s 48.724us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 14.570s 3855.460us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * 1 test run
uart_noise_filter 89789422386867411747719821730737901789481481596588715280828843193746557953308 80
UVM_ERROR @ 1609739626 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 1609779626 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 1886499626 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 1886499626 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0