Simulation Results: adc_ctrl

 
06/05/2026 15:30:23 DVSim: v1.34.0 sha: 238ca4d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 64.71 %
  • code
  • 91.53 %
  • assert
  • 91.09 %
  • func
  • 11.52 %
  • line
  • 97.94 %
  • branch
  • 96.16 %
  • cond
  • 85.40 %
  • toggle
  • 99.76 %
  • FSM
  • 78.38 %
Validation stages
V1
100.00%
V2
52.63%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 4.230s 5987.811us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 3.390s 1156.965us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 1.040s 386.948us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 32.910s 26664.681us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 1.850s 802.729us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.370s 333.861us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 1.040s 386.948us 1 1 100.00
adc_ctrl_csr_aliasing 1.850s 802.729us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 0 1 0.00
adc_ctrl_filters_polled 1.600s 469.918us 0 1 0.00
filters_polled_fixed 0 1 0.00
adc_ctrl_filters_polled_fixed 1.030s 501.104us 0 1 0.00
filters_interrupt 0 1 0.00
adc_ctrl_filters_interrupt 1.390s 426.217us 0 1 0.00
filters_interrupt_fixed 0 1 0.00
adc_ctrl_filters_interrupt_fixed 1.100s 309.908us 0 1 0.00
filters_wakeup 0 1 0.00
adc_ctrl_filters_wakeup 0.710s 474.428us 0 1 0.00
filters_wakeup_fixed 0 1 0.00
adc_ctrl_filters_wakeup_fixed 0.750s 300.475us 0 1 0.00
filters_both 0 1 0.00
adc_ctrl_filters_both 0.800s 428.729us 0 1 0.00
clock_gating 0 1 0.00
adc_ctrl_clock_gating 1.140s 513.685us 0 1 0.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 6.570s 3836.542us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 55.450s 33848.262us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 53.090s 106934.548us 1 1 100.00
stress_all 0 1 0.00
adc_ctrl_stress_all 2.570s 1216.861us 0 1 0.00
alert_test 1 1 100.00
adc_ctrl_alert_test 0.940s 320.635us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 0.880s 405.754us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 1.770s 396.864us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 1.770s 396.864us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 3.390s 1156.965us 1 1 100.00
adc_ctrl_csr_rw 1.040s 386.948us 1 1 100.00
adc_ctrl_csr_aliasing 1.850s 802.729us 1 1 100.00
adc_ctrl_same_csr_outstanding 5.180s 2655.283us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 3.390s 1156.965us 1 1 100.00
adc_ctrl_csr_rw 1.040s 386.948us 1 1 100.00
adc_ctrl_csr_aliasing 1.850s 802.729us 1 1 100.00
adc_ctrl_same_csr_outstanding 5.180s 2655.283us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 14.660s 8537.064us 1 1 100.00
adc_ctrl_tl_intg_err 10.550s 4316.442us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 10.550s 4316.442us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
adc_ctrl_stress_all_with_rand_reset 1.120s 1005.573us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [*, *] 10 test runs
adc_ctrl_filters_polled 72895304161096599115887668633685980645773131595149504912888639832006145220671 389
UVM_INFO @ 469917592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 80769162655793462490465595253121869989045793874741809238048282600583129357675 389
UVM_INFO @ 501104033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 46318685116335812729662620882179040651356795371663086173716561258536459794515 389
UVM_INFO @ 426217324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 70830478381228967878372278890800188881004230014711139243868396962661308990856 389
UVM_INFO @ 309908277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 42934560414556483685940440774038676587078029782872788223969382099434592685893 389
UVM_INFO @ 474427723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 75892224891515496912660184183167687209379790196882374109889841088715913091766 389
UVM_INFO @ 300475093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 5549924814879531717900537546787611201630090202710875858923904992944065448736 389
UVM_INFO @ 513684686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 25605972138585388928702444487541527052325915731897087270794303209391322238928 389
UVM_INFO @ 428729487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 5372703659808189312719764562320397636730050623741099249476333334756955835332 409
UVM_INFO @ 1005573496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 80521337783147784938121436212240634540443817399535348389636311823394055741138 400
UVM_INFO @ 1216861370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---