Simulation Results: aes/masked

 
06/05/2026 15:30:23 DVSim: v1.34.0 sha: 238ca4d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.15 %
  • code
  • 94.28 %
  • assert
  • 98.23 %
  • func
  • 71.95 %
  • block
  • 94.43 %
  • line
  • 96.02 %
  • branch
  • 87.54 %
  • toggle
  • 97.99 %
  • FSM
  • 95.56 %
Validation stages
V1
100.00%
V2
88.24%
V2S
81.25%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 75.488us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 85.336us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 89.172us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 70.428us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 3.000s 117.775us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 538.917us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 81.565us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 70.428us 1 1 100.00
aes_csr_aliasing 3.000s 538.917us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 85.336us 1 1 100.00
aes_config_error 3.000s 125.129us 1 1 100.00
aes_stress 24.000s 4124.883us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 85.336us 1 1 100.00
aes_config_error 3.000s 125.129us 1 1 100.00
aes_stress 24.000s 4124.883us 1 1 100.00
back2back 2 2 100.00
aes_stress 24.000s 4124.883us 1 1 100.00
aes_b2b 9.000s 532.893us 1 1 100.00
backpressure 1 1 100.00
aes_stress 24.000s 4124.883us 1 1 100.00
multi_message 3 4 75.00
aes_smoke 3.000s 85.336us 1 1 100.00
aes_config_error 3.000s 125.129us 1 1 100.00
aes_stress 24.000s 4124.883us 1 1 100.00
aes_alert_reset 27.000s 10033.654us 0 1 0.00
failure_test 2 3 66.67
aes_man_cfg_err 2.000s 65.251us 1 1 100.00
aes_config_error 3.000s 125.129us 1 1 100.00
aes_alert_reset 27.000s 10033.654us 0 1 0.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 66.946us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 6.000s 955.745us 1 1 100.00
reset_recovery 0 1 0.00
aes_alert_reset 27.000s 10033.654us 0 1 0.00
stress 1 1 100.00
aes_stress 24.000s 4124.883us 1 1 100.00
sideload 2 2 100.00
aes_stress 24.000s 4124.883us 1 1 100.00
aes_sideload 3.000s 86.093us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 91.914us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 54.000s 10034.224us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 2.000s 56.851us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 141.288us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 141.288us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 89.172us 1 1 100.00
aes_csr_rw 2.000s 70.428us 1 1 100.00
aes_csr_aliasing 3.000s 538.917us 1 1 100.00
aes_same_csr_outstanding 2.000s 69.437us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 89.172us 1 1 100.00
aes_csr_rw 2.000s 70.428us 1 1 100.00
aes_csr_aliasing 3.000s 538.917us 1 1 100.00
aes_same_csr_outstanding 2.000s 69.437us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 3.000s 200.122us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 50.000s 10008.261us 0 1 0.00
aes_control_fi 3.000s 47.564us 1 1 100.00
aes_cipher_fi 3.000s 45.943us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 1.000s 83.546us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 1.000s 83.546us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 1.000s 83.546us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 1.000s 83.546us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
aes_shadow_reg_errors_with_csr_rw 3.000s 770.808us 0 1 0.00
tl_intg_err 2 2 100.00
aes_sec_cm 3.000s 231.189us 1 1 100.00
aes_tl_intg_err 2.000s 365.287us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 365.287us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 0 1 0.00
aes_alert_reset 27.000s 10033.654us 0 1 0.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 83.546us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 83.546us 1 1 100.00
sec_cm_main_config_sparse 3 4 75.00
aes_smoke 3.000s 85.336us 1 1 100.00
aes_stress 24.000s 4124.883us 1 1 100.00
aes_alert_reset 27.000s 10033.654us 0 1 0.00
aes_core_fi 3.000s 125.856us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 3.000s 125.129us 1 1 100.00
aes_stress 24.000s 4124.883us 1 1 100.00
aes_core_fi 3.000s 125.856us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 83.546us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 87.217us 1 1 100.00
aes_stress 24.000s 4124.883us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 24.000s 4124.883us 1 1 100.00
aes_sideload 3.000s 86.093us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 87.217us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 87.217us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 87.217us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 87.217us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 87.217us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 24.000s 4124.883us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 24.000s 4124.883us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 50.000s 10008.261us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 50.000s 10008.261us 0 1 0.00
aes_control_fi 3.000s 47.564us 1 1 100.00
aes_cipher_fi 3.000s 45.943us 1 1 100.00
aes_ctr_fi 2.000s 138.114us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 50.000s 10008.261us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 50.000s 10008.261us 0 1 0.00
aes_control_fi 3.000s 47.564us 1 1 100.00
aes_cipher_fi 3.000s 45.943us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 3.000s 45.943us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 50.000s 10008.261us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 50.000s 10008.261us 0 1 0.00
aes_control_fi 3.000s 47.564us 1 1 100.00
aes_ctr_fi 2.000s 138.114us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 50.000s 10008.261us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 50.000s 10008.261us 0 1 0.00
aes_control_fi 3.000s 47.564us 1 1 100.00
aes_cipher_fi 3.000s 45.943us 1 1 100.00
aes_ctr_fi 2.000s 138.114us 1 1 100.00
sec_cm_main_fsm_global_esc 0 1 0.00
aes_alert_reset 27.000s 10033.654us 0 1 0.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 50.000s 10008.261us 0 1 0.00
aes_control_fi 3.000s 47.564us 1 1 100.00
aes_cipher_fi 3.000s 45.943us 1 1 100.00
aes_ctr_fi 2.000s 138.114us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 50.000s 10008.261us 0 1 0.00
aes_control_fi 3.000s 47.564us 1 1 100.00
aes_cipher_fi 3.000s 45.943us 1 1 100.00
aes_ctr_fi 2.000s 138.114us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 50.000s 10008.261us 0 1 0.00
aes_control_fi 3.000s 47.564us 1 1 100.00
aes_ctr_fi 2.000s 138.114us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 50.000s 10008.261us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 50.000s 10008.261us 0 1 0.00
aes_control_fi 3.000s 47.564us 1 1 100.00
aes_cipher_fi 3.000s 45.943us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 11.000s 340.710us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:454) [aes_alert_reset_vseq] wait timeout occurred! 2 test runs
aes_alert_reset 43546902920781151318390726860101549566949430854475727744532529792684811672207 716
UVM_INFO @ 10033653974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all 45509583083687279435275393094025969312675918800025545247891855904342365335407 8770
UVM_INFO @ 10034224397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [aes_fi_vseq] wait timeout occurred! 1 test run
aes_fi 67577098385975310508456382198547739322721252818904011296514300901641409964485 2537
UVM_INFO @ 10008261182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:76) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 1 test run
aes_stress_all_with_rand_reset 79636974262784440120347673554848080855377194160707225557887681510342496518867 218
UVM_INFO @ 340709527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: aes_reg_block_extended.ctrl_shadowed reset value: * 1 test run
aes_shadow_reg_errors_with_csr_rw 55089681658879649943604499857752644042916199521008231463344767947003892861730 107
UVM_INFO @ 770807860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---