Simulation Results: aes/unmasked

 
06/05/2026 15:30:23 DVSim: v1.34.0 sha: 238ca4d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.76 %
  • code
  • 89.64 %
  • assert
  • 97.73 %
  • func
  • 72.92 %
  • block
  • 90.21 %
  • line
  • 92.69 %
  • branch
  • 81.22 %
  • toggle
  • 97.99 %
  • FSM
  • 86.67 %
Validation stages
V1
100.00%
V2
88.24%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 1.000s 56.454us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 75.815us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 71.234us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 66.720us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 6.000s 970.173us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 299.064us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 90.242us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 66.720us 1 1 100.00
aes_csr_aliasing 3.000s 299.064us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 75.815us 1 1 100.00
aes_config_error 2.000s 96.398us 1 1 100.00
aes_stress 2.000s 97.996us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 75.815us 1 1 100.00
aes_config_error 2.000s 96.398us 1 1 100.00
aes_stress 2.000s 97.996us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 97.996us 1 1 100.00
aes_b2b 3.000s 108.249us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 97.996us 1 1 100.00
multi_message 3 4 75.00
aes_smoke 2.000s 75.815us 1 1 100.00
aes_config_error 2.000s 96.398us 1 1 100.00
aes_stress 2.000s 97.996us 1 1 100.00
aes_alert_reset 26.000s 10030.491us 0 1 0.00
failure_test 2 3 66.67
aes_man_cfg_err 1.000s 63.671us 1 1 100.00
aes_config_error 2.000s 96.398us 1 1 100.00
aes_alert_reset 26.000s 10030.491us 0 1 0.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 181.282us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 4.000s 463.415us 1 1 100.00
reset_recovery 0 1 0.00
aes_alert_reset 26.000s 10030.491us 0 1 0.00
stress 1 1 100.00
aes_stress 2.000s 97.996us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 97.996us 1 1 100.00
aes_sideload 2.000s 129.048us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 142.087us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 24.000s 10403.835us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 1.000s 56.913us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 87.345us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 87.345us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 71.234us 1 1 100.00
aes_csr_rw 2.000s 66.720us 1 1 100.00
aes_csr_aliasing 3.000s 299.064us 1 1 100.00
aes_same_csr_outstanding 1.000s 58.896us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 71.234us 1 1 100.00
aes_csr_rw 2.000s 66.720us 1 1 100.00
aes_csr_aliasing 3.000s 299.064us 1 1 100.00
aes_same_csr_outstanding 1.000s 58.896us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 2.000s 58.890us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 9.000s 10052.968us 0 1 0.00
aes_control_fi 2.000s 87.291us 1 1 100.00
aes_cipher_fi 2.000s 55.135us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 113.652us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 113.652us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 113.652us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 113.652us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 77.700us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 3.000s 1439.157us 1 1 100.00
aes_tl_intg_err 2.000s 266.937us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 266.937us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 0 1 0.00
aes_alert_reset 26.000s 10030.491us 0 1 0.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 113.652us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 113.652us 1 1 100.00
sec_cm_main_config_sparse 3 4 75.00
aes_smoke 2.000s 75.815us 1 1 100.00
aes_stress 2.000s 97.996us 1 1 100.00
aes_alert_reset 26.000s 10030.491us 0 1 0.00
aes_core_fi 2.000s 397.142us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 2.000s 96.398us 1 1 100.00
aes_stress 2.000s 97.996us 1 1 100.00
aes_core_fi 2.000s 397.142us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 113.652us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 86.564us 1 1 100.00
aes_stress 2.000s 97.996us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 97.996us 1 1 100.00
aes_sideload 2.000s 129.048us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 86.564us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 86.564us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 86.564us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 86.564us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 86.564us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 97.996us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 97.996us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 9.000s 10052.968us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 9.000s 10052.968us 0 1 0.00
aes_control_fi 2.000s 87.291us 1 1 100.00
aes_cipher_fi 2.000s 55.135us 1 1 100.00
aes_ctr_fi 1.000s 74.482us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 9.000s 10052.968us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 9.000s 10052.968us 0 1 0.00
aes_control_fi 2.000s 87.291us 1 1 100.00
aes_cipher_fi 2.000s 55.135us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 55.135us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 9.000s 10052.968us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 9.000s 10052.968us 0 1 0.00
aes_control_fi 2.000s 87.291us 1 1 100.00
aes_ctr_fi 1.000s 74.482us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 9.000s 10052.968us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 9.000s 10052.968us 0 1 0.00
aes_control_fi 2.000s 87.291us 1 1 100.00
aes_cipher_fi 2.000s 55.135us 1 1 100.00
aes_ctr_fi 1.000s 74.482us 1 1 100.00
sec_cm_main_fsm_global_esc 0 1 0.00
aes_alert_reset 26.000s 10030.491us 0 1 0.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 9.000s 10052.968us 0 1 0.00
aes_control_fi 2.000s 87.291us 1 1 100.00
aes_cipher_fi 2.000s 55.135us 1 1 100.00
aes_ctr_fi 1.000s 74.482us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 9.000s 10052.968us 0 1 0.00
aes_control_fi 2.000s 87.291us 1 1 100.00
aes_cipher_fi 2.000s 55.135us 1 1 100.00
aes_ctr_fi 1.000s 74.482us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 9.000s 10052.968us 0 1 0.00
aes_control_fi 2.000s 87.291us 1 1 100.00
aes_ctr_fi 1.000s 74.482us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 9.000s 10052.968us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 9.000s 10052.968us 0 1 0.00
aes_control_fi 2.000s 87.291us 1 1 100.00
aes_cipher_fi 2.000s 55.135us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 23.000s 827.650us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:454) [aes_alert_reset_vseq] wait timeout occurred! 2 test runs
aes_alert_reset 98707901140928152985226776503537079477748921299288617287303860839730032716277 1717
UVM_INFO @ 10030491155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all 87400118779392308242916841982637720819460751397565175508857125655650872472611 13083
UVM_INFO @ 10403835095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [aes_fi_vseq] wait timeout occurred! 1 test run
aes_fi 2423034866191925628039963221776301799319460572796769412390611068063731005724 2617
UVM_INFO @ 10052968244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_stress_all_with_rand_reset 30103613960884585529402938435011663039069106410215726341014524454687749748290 1810
UVM_INFO @ 827650500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---