Simulation Results: alert_handler

 
06/05/2026 15:30:23 DVSim: v1.34.0 sha: 238ca4d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.83 %
  • code
  • 91.95 %
  • assert
  • 98.14 %
  • func
  • 79.41 %
  • line
  • 99.70 %
  • branch
  • 98.33 %
  • cond
  • 91.37 %
  • toggle
  • 92.91 %
  • FSM
  • 77.42 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 37.030s 3975.900us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 5.670s 396.014us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 2.450s 63.755us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 129.250s 3713.234us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 47.360s 2371.514us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 6.580s 136.611us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 2.450s 63.755us 1 1 100.00
alert_handler_csr_aliasing 47.360s 2371.514us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 178.630s 39006.266us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 10.690s 1351.115us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 1346.590s 136680.103us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 10.070s 745.213us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 37.030s 3975.900us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 39.580s 1059.736us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 17.110s 1139.410us 1 1 100.00
ping_timeout 1 1 100.00
alert_handler_ping_timeout 140.200s 17402.208us 1 1 100.00
lpg 2 2 100.00
alert_handler_lpg 1345.590s 67887.356us 1 1 100.00
alert_handler_lpg_stub_clk 1077.080s 281102.339us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 6.090s 642.425us 1 1 100.00
alert_handler_entropy_stress_test 1 1 100.00
alert_handler_entropy_stress 28.270s 4276.330us 1 1 100.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 1.800s 20.519us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.280s 8.119us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 11.330s 1315.007us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 11.330s 1315.007us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 5.670s 396.014us 1 1 100.00
alert_handler_csr_rw 2.450s 63.755us 1 1 100.00
alert_handler_csr_aliasing 47.360s 2371.514us 1 1 100.00
alert_handler_same_csr_outstanding 24.130s 518.559us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 5.670s 396.014us 1 1 100.00
alert_handler_csr_rw 2.450s 63.755us 1 1 100.00
alert_handler_csr_aliasing 47.360s 2371.514us 1 1 100.00
alert_handler_same_csr_outstanding 24.130s 518.559us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 186.850s 4407.954us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 186.850s 4407.954us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 186.850s 4407.954us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 186.850s 4407.954us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 221.280s 2638.157us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 13.940s 1245.609us 1 1 100.00
alert_handler_tl_intg_err 27.540s 3358.009us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 27.540s 3358.009us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 186.850s 4407.954us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 37.030s 3975.900us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 37.030s 3975.900us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 37.030s 3975.900us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 37.030s 3975.900us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 10.070s 745.213us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 1345.590s 67887.356us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 10.070s 745.213us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1346.590s 136680.103us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1346.590s 136680.103us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 13.940s 1245.609us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 13.940s 1245.609us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 13.940s 1245.609us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 13.940s 1245.609us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 13.940s 1245.609us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 13.940s 1245.609us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 13.940s 1245.609us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 13.940s 1245.609us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 13.940s 1245.609us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 32.650s 904.429us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 65644764200316167054327709934246828481820340564144587217875886028920503339802 97
UVM_INFO @ 904428703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---