Simulation Results: chip

 
06/05/2026 15:30:23 DVSim: v1.34.0 sha: 238ca4d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 73.48 %
  • code
  • 85.00 %
  • assert
  • 97.37 %
  • func
  • 38.07 %
  • line
  • 94.31 %
  • branch
  • 93.51 %
  • cond
  • 88.89 %
  • toggle
  • 91.14 %
  • FSM
  • 57.14 %
Validation stages
V1
94.44%
V2
78.78%
V2S
100.00%
V3
65.38%
unmapped
80.00%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 4 4 100.00
chip_sw_example_flash 148.670s 2656.685us 1 1 100.00
chip_sw_example_rom 65.510s 2061.527us 1 1 100.00
chip_sw_example_manufacturer 164.200s 2586.503us 1 1 100.00
chip_sw_example_concurrency 151.580s 2966.646us 1 1 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 182.140s 4714.960us 1 1 100.00
csr_rw 1 1 100.00
chip_csr_rw 382.930s 5919.341us 1 1 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 694.870s 7870.012us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 5517.390s 38283.286us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
chip_csr_mem_rw_with_rand_reset 58.500s 2238.730us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
chip_csr_aliasing 5517.390s 38283.286us 1 1 100.00
chip_csr_rw 382.930s 5919.341us 1 1 100.00
xbar_smoke 1 1 100.00
xbar_smoke 5.720s 53.687us 1 1 100.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 269.340s 4597.858us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 269.340s 4597.858us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 269.340s 4597.858us 1 1 100.00
chip_sw_uart_tx_rx 1 1 100.00
chip_sw_uart_tx_rx 345.720s 5155.792us 1 1 100.00
chip_sw_uart_rx_overflow 4 4 100.00
chip_sw_uart_tx_rx 345.720s 5155.792us 1 1 100.00
chip_sw_uart_tx_rx_idx1 346.460s 4648.695us 1 1 100.00
chip_sw_uart_tx_rx_idx2 378.130s 4059.360us 1 1 100.00
chip_sw_uart_tx_rx_idx3 378.670s 4468.443us 1 1 100.00
chip_sw_uart_baud_rate 1 1 100.00
chip_sw_uart_rand_baudrate 408.670s 4297.057us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2 2 100.00
chip_sw_uart_tx_rx_alt_clk_freq 1785.350s 13689.006us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 284.640s 4441.267us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 1 1 100.00
chip_padctrl_attributes 202.860s 5500.974us 1 1 100.00
chip_padctrl_attributes 1 1 100.00
chip_padctrl_attributes 202.860s 5500.974us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 172.500s 3185.154us 1 1 100.00
chip_sw_sleep_pin_wake 0 1 0.00
chip_sw_sleep_pin_wake 126.700s 2857.620us 0 1 0.00
chip_sw_sleep_pin_retention 1 1 100.00
chip_sw_sleep_pin_retention 144.140s 2536.832us 1 1 100.00
chip_sw_tap_strap_sampling 4 4 100.00
chip_tap_straps_dev 912.150s 15285.479us 1 1 100.00
chip_tap_straps_testunlock0 140.420s 3602.243us 1 1 100.00
chip_tap_straps_rma 343.230s 5749.134us 1 1 100.00
chip_tap_straps_prod 85.820s 2337.577us 1 1 100.00
chip_sw_pattgen_ios 1 1 100.00
chip_sw_pattgen_ios 154.620s 2861.633us 1 1 100.00
chip_sw_sleep_pwm_pulses 1 1 100.00
chip_sw_sleep_pwm_pulses 810.410s 9399.652us 1 1 100.00
chip_sw_data_integrity 1 1 100.00
chip_sw_data_integrity_escalation 414.840s 5891.805us 1 1 100.00
chip_sw_instruction_integrity 1 1 100.00
chip_sw_data_integrity_escalation 414.840s 5891.805us 1 1 100.00
chip_sw_ast_clk_outputs 1 1 100.00
chip_sw_ast_clk_outputs 630.760s 7323.609us 1 1 100.00
chip_sw_ast_clk_rst_inputs 0 1 0.00
chip_sw_ast_clk_rst_inputs 1091.780s 11149.949us 0 1 0.00
chip_sw_ast_sys_clk_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 365.170s 4337.437us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 590.770s 5537.858us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3670.220s 19526.534us 1 1 100.00
chip_sw_aes_enc_jitter_en 162.410s 2995.594us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 681.390s 6720.353us 1 1 100.00
chip_sw_hmac_enc_jitter_en 194.560s 3006.438us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1644.150s 13340.390us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 149.940s 2575.583us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 393.530s 5671.581us 1 1 100.00
chip_sw_clkmgr_jitter 164.890s 3353.220us 1 1 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 178.300s 3168.694us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 2 2 100.00
chip_sw_sensor_ctrl_alert 374.720s 7151.991us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 201.900s 5175.620us 1 1 100.00
chip_sw_sensor_ctrl_ast_status 1 1 100.00
chip_sw_sensor_ctrl_status 185.440s 3089.785us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 201.900s 5175.620us 1 1 100.00
chip_sw_smoketest 17 17 100.00
chip_sw_flash_scrambling_smoketest 142.020s 2485.138us 1 1 100.00
chip_sw_aes_smoketest 159.290s 3185.372us 1 1 100.00
chip_sw_aon_timer_smoketest 178.780s 3584.247us 1 1 100.00
chip_sw_clkmgr_smoketest 145.650s 2632.500us 1 1 100.00
chip_sw_csrng_smoketest 164.660s 3475.593us 1 1 100.00
chip_sw_entropy_src_smoketest 709.380s 6108.035us 1 1 100.00
chip_sw_gpio_smoketest 232.850s 3319.563us 1 1 100.00
chip_sw_hmac_smoketest 160.690s 2548.831us 1 1 100.00
chip_sw_kmac_smoketest 182.690s 3244.368us 1 1 100.00
chip_sw_otbn_smoketest 1625.770s 11483.549us 1 1 100.00
chip_sw_pwrmgr_smoketest 305.160s 5588.296us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 232.550s 5480.911us 1 1 100.00
chip_sw_rv_plic_smoketest 140.880s 2546.883us 1 1 100.00
chip_sw_rv_timer_smoketest 170.100s 3351.840us 1 1 100.00
chip_sw_rstmgr_smoketest 192.350s 3177.232us 1 1 100.00
chip_sw_sram_ctrl_smoketest 155.360s 2612.704us 1 1 100.00
chip_sw_uart_smoketest 200.660s 3579.767us 1 1 100.00
chip_sw_otp_smoketest 1 1 100.00
chip_sw_otp_ctrl_smoketest 119.890s 2379.530us 1 1 100.00
chip_sw_rom_functests 0 1 0.00
rom_keymgr_functest 313.570s 4968.461us 0 1 0.00
chip_sw_boot 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 8037.900s 64447.726us 1 1 100.00
chip_sw_secure_boot 1 1 100.00
rom_e2e_smoke 2955.650s 15307.613us 1 1 100.00
chip_sw_rom_raw_unlock 0 1 0.00
rom_raw_unlock 37.242s 0.000us 0 1 0.00
chip_sw_power_idle_load 0 1 0.00
chip_sw_power_idle_load 230.180s 3389.285us 0 1 0.00
chip_sw_power_sleep_load 0 1 0.00
chip_sw_power_sleep_load 231.980s 3738.357us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 1 1 100.00
chip_sw_exit_test_unlocked_bootstrap 7490.500s 55263.088us 1 1 100.00
chip_sw_inject_scramble_seed 1 1 100.00
chip_sw_inject_scramble_seed 7268.130s 59289.104us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 74.030s 2432.247us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 74.030s 2432.247us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
chip_csr_aliasing 5517.390s 38283.286us 1 1 100.00
chip_same_csr_outstanding 3000.430s 29006.149us 1 1 100.00
chip_csr_hw_reset 182.140s 4714.960us 1 1 100.00
chip_csr_rw 382.930s 5919.341us 1 1 100.00
tl_d_partial_access 4 4 100.00
chip_csr_aliasing 5517.390s 38283.286us 1 1 100.00
chip_same_csr_outstanding 3000.430s 29006.149us 1 1 100.00
chip_csr_hw_reset 182.140s 4714.960us 1 1 100.00
chip_csr_rw 382.930s 5919.341us 1 1 100.00
xbar_base_random_sequence 1 1 100.00
xbar_random 29.090s 407.166us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 7.520s 48.458us 1 1 100.00
xbar_smoke_large_delays 44.320s 6707.506us 1 1 100.00
xbar_smoke_slow_rsp 50.560s 5446.982us 1 1 100.00
xbar_random_zero_delays 12.500s 167.438us 1 1 100.00
xbar_random_large_delays 219.580s 37831.050us 1 1 100.00
xbar_random_slow_rsp 202.710s 23497.808us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 8.680s 225.234us 1 1 100.00
xbar_error_and_unmapped_addr 14.190s 192.935us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 31.000s 597.231us 1 1 100.00
xbar_error_and_unmapped_addr 14.190s 192.935us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 50.730s 2006.852us 1 1 100.00
xbar_access_same_device_slow_rsp 258.510s 29860.933us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 50.340s 2664.016us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 118.490s 1948.919us 1 1 100.00
xbar_stress_all_with_error 71.260s 1341.641us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 387.340s 9280.182us 1 1 100.00
xbar_stress_all_with_reset_error 92.110s 622.918us 1 1 100.00
rom_e2e_smoke 1 1 100.00
rom_e2e_smoke 2955.650s 15307.613us 1 1 100.00
rom_e2e_shutdown_output 1 1 100.00
rom_e2e_shutdown_output 2695.310s 29364.444us 1 1 100.00
rom_e2e_shutdown_exception_c 1 1 100.00
rom_e2e_shutdown_exception_c 2901.710s 16345.091us 1 1 100.00
rom_e2e_boot_policy_valid 0 15 0.00
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 42.628s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 7.603s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 9.631s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 12.416s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 10.174s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 50.456s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 90.672s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 75.285s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 37.191s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 10.577s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 124.142s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 88.449s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 51.308s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 60.059s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 45.660s 0.000us 0 1 0.00
rom_e2e_sigverify_always 0 15 0.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 16.310s 10.200us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 17.400s 10.320us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 17.360s 10.200us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 16.940s 10.120us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 18.370s 10.400us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 16.360s 10.220us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 17.100s 10.240us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 18.350s 10.160us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 17.870s 10.400us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 17.840s 10.340us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 17.080s 10.320us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 18.350s 10.380us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 17.160s 10.340us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 16.950s 10.380us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 20.620s 10.160us 0 1 0.00
rom_e2e_asm_init 0 5 0.00
rom_e2e_asm_init_test_unlocked0 56.946s 0.000us 0 1 0.00
rom_e2e_asm_init_dev 69.961s 0.000us 0 1 0.00
rom_e2e_asm_init_prod 112.476s 0.000us 0 1 0.00
rom_e2e_asm_init_prod_end 63.882s 0.000us 0 1 0.00
rom_e2e_asm_init_rma 67.905s 0.000us 0 1 0.00
rom_e2e_keymgr_init 3 3 100.00
rom_e2e_keymgr_init_rom_ext_meas 5951.420s 29566.794us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_no_meas 5935.990s 29321.752us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 5843.710s 28906.685us 1 1 100.00
rom_e2e_static_critical 1 1 100.00
rom_e2e_static_critical 3286.310s 16838.891us 1 1 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3058.740s 34539.327us 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3058.740s 34539.327us 0 1 0.00
chip_sw_aes_enc 2 2 100.00
chip_sw_aes_enc 177.530s 3320.791us 1 1 100.00
chip_sw_aes_enc_jitter_en 162.410s 2995.594us 1 1 100.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 115.090s 2840.344us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 142.450s 2340.042us 1 1 100.00
chip_sw_aes_sideload 1 1 100.00
chip_sw_keymgr_sideload_aes 741.130s 8292.070us 1 1 100.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 145.830s 3529.109us 0 1 0.00
chip_sw_alert_handler_escalations 1 1 100.00
chip_sw_alert_handler_escalation 309.600s 5046.108us 1 1 100.00
chip_sw_all_escalation_resets 1 1 100.00
chip_sw_all_escalation_resets 416.890s 5504.898us 1 1 100.00
chip_sw_alert_handler_irqs 3 3 100.00
chip_plic_all_irqs_0 574.910s 5177.612us 1 1 100.00
chip_plic_all_irqs_10 231.530s 3338.079us 1 1 100.00
chip_plic_all_irqs_20 396.950s 3858.410us 1 1 100.00
chip_sw_alert_handler_entropy 1 1 100.00
chip_sw_alert_handler_entropy 175.650s 3517.758us 1 1 100.00
chip_sw_alert_handler_crashdump 1 1 100.00
chip_sw_rstmgr_alert_info 1042.900s 10445.407us 1 1 100.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 316.830s 4878.456us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 122.840s 2891.071us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 14400.142s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 856.030s 7680.547us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1069.810s 8614.901us 1 1 100.00
chip_sw_alert_handler_ping_ok 1 1 100.00
chip_sw_alert_handler_ping_ok 769.290s 7575.490us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 8665.320s 254897.618us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 1 1 100.00
chip_sw_aon_timer_irq 235.950s 4204.665us 1 1 100.00
chip_sw_aon_timer_sleep_wakeup 1 1 100.00
chip_sw_pwrmgr_smoketest 305.160s 5588.296us 1 1 100.00
chip_sw_aon_timer_wdog_bark_irq 1 1 100.00
chip_sw_aon_timer_irq 235.950s 4204.665us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 492.900s 7812.034us 1 1 100.00
chip_sw_aon_timer_sleep_wdog_bite_reset 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 492.900s 7812.034us 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 354.370s 6502.362us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 338.930s 5078.888us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 562.190s 5713.271us 1 1 100.00
chip_sw_aes_idle 142.450s 2340.042us 1 1 100.00
chip_sw_hmac_enc_idle 176.930s 3342.421us 1 1 100.00
chip_sw_kmac_idle 180.610s 3605.792us 1 1 100.00
chip_sw_clkmgr_off_trans 4 4 100.00
chip_sw_clkmgr_off_aes_trans 314.010s 3837.124us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 285.940s 4675.672us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 273.160s 4826.253us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 333.810s 4563.333us 1 1 100.00
chip_sw_clkmgr_off_peri 1 1 100.00
chip_sw_clkmgr_off_peri 692.800s 8603.375us 1 1 100.00
chip_sw_clkmgr_div 7 7 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 381.670s 4291.024us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 378.130s 4972.678us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 387.610s 4139.847us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 409.600s 4946.073us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 371.710s 3900.569us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 360.400s 4580.175us 1 1 100.00
chip_sw_ast_clk_outputs 630.760s 7323.609us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 697.140s 12509.834us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw 2 2 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 387.610s 4139.847us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 409.600s 4946.073us 1 1 100.00
chip_sw_clkmgr_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 365.170s 4337.437us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 590.770s 5537.858us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3670.220s 19526.534us 1 1 100.00
chip_sw_aes_enc_jitter_en 162.410s 2995.594us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 681.390s 6720.353us 1 1 100.00
chip_sw_hmac_enc_jitter_en 194.560s 3006.438us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1644.150s 13340.390us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 149.940s 2575.583us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 393.530s 5671.581us 1 1 100.00
chip_sw_clkmgr_jitter 164.890s 3353.220us 1 1 100.00
chip_sw_clkmgr_extended_range 11 11 100.00
chip_sw_clkmgr_jitter_reduced_freq 145.520s 3096.585us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 401.090s 4188.187us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 710.920s 7658.301us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 3811.500s 25511.923us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 147.180s 3032.156us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 165.110s 3031.721us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 975.200s 10047.520us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 177.980s 3195.317us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 359.510s 5752.370us 1 1 100.00
chip_sw_flash_init_reduced_freq 1281.750s 23373.718us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 2633.550s 22998.982us 1 1 100.00
chip_sw_clkmgr_deep_sleep_frequency 1 1 100.00
chip_sw_ast_clk_outputs 630.760s 7323.609us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 1 1 100.00
chip_sw_clkmgr_sleep_frequency 370.860s 4533.556us 1 1 100.00
chip_sw_clkmgr_reset_frequency 1 1 100.00
chip_sw_clkmgr_reset_frequency 236.630s 3366.799us 1 1 100.00
chip_sw_clkmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 416.890s 5504.898us 1 1 100.00
chip_sw_clkmgr_alert_handler_clock_enables 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 856.030s 7680.547us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 2177.180s 24073.689us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 0 1 0.00
chip_sw_csrng_fuse_en_sw_app_read_test 156.990s 2901.381us 0 1 0.00
chip_sw_csrng_lc_hw_debug_en 1 1 100.00
chip_sw_csrng_lc_hw_debug_en_test 502.200s 6839.459us 1 1 100.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 128.550s 2746.314us 1 1 100.00
chip_sw_edn_entropy_reqs 3 3 100.00
chip_sw_csrng_edn_concurrency 3738.750s 23074.804us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 113.220s 2628.804us 1 1 100.00
chip_sw_edn_entropy_reqs 644.030s 6321.676us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 1 1 100.00
chip_sw_entropy_src_ast_rng_req 113.220s 2628.804us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 2177.180s 24073.689us 1 1 100.00
chip_sw_entropy_src_known_answer_tests 1 1 100.00
chip_sw_entropy_src_kat_test 166.110s 2949.130us 1 1 100.00
chip_sw_flash_init 1 1 100.00
chip_sw_flash_init 1413.360s 22195.852us 1 1 100.00
chip_sw_flash_host_access 2 2 100.00
chip_sw_flash_ctrl_access 560.980s 5569.862us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 590.770s 5537.858us 1 1 100.00
chip_sw_flash_ctrl_ops 2 2 100.00
chip_sw_flash_ctrl_ops 405.920s 4293.877us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en 365.170s 4337.437us 1 1 100.00
chip_sw_flash_rma_unlocked 1 1 100.00
chip_sw_flash_rma_unlocked 3495.010s 43586.070us 1 1 100.00
chip_sw_flash_scramble 1 1 100.00
chip_sw_flash_init 1413.360s 22195.852us 1 1 100.00
chip_sw_flash_idle_low_power 1 1 100.00
chip_sw_flash_ctrl_idle_low_power 204.030s 3515.987us 1 1 100.00
chip_sw_flash_keymgr_seeds 1 1 100.00
chip_sw_keymgr_key_derivation 589.270s 6310.391us 1 1 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 132.520s 3168.919us 0 1 0.00
chip_sw_flash_creator_seed_wipe_on_rma 1 1 100.00
chip_sw_flash_rma_unlocked 3495.010s 43586.070us 1 1 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 132.520s 3168.919us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 132.520s 3168.919us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_wr_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 132.520s 3168.919us 0 1 0.00
chip_sw_flash_lc_seed_hw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 132.520s 3168.919us 0 1 0.00
chip_sw_flash_lc_escalate_en 1 1 100.00
chip_sw_all_escalation_resets 416.890s 5504.898us 1 1 100.00
chip_sw_flash_prim_tl_access 1 1 100.00
chip_prim_tl_access 461.480s 13631.693us 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 636.900s 5040.986us 1 1 100.00
chip_sw_flash_ctrl_escalation_reset 1 1 100.00
chip_sw_flash_crash_alert 408.320s 6458.835us 1 1 100.00
chip_sw_flash_ctrl_write_clear 1 1 100.00
chip_sw_flash_crash_alert 408.320s 6458.835us 1 1 100.00
chip_sw_hmac_enc 2 2 100.00
chip_sw_hmac_enc 182.090s 3397.085us 1 1 100.00
chip_sw_hmac_enc_jitter_en 194.560s 3006.438us 1 1 100.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 176.930s 3342.421us 1 1 100.00
chip_sw_hmac_all_configurations 1 1 100.00
chip_sw_hmac_oneshot 1444.480s 10510.264us 1 1 100.00
chip_sw_hmac_multistream_mode 1 1 100.00
chip_sw_hmac_multistream 719.910s 5588.834us 1 1 100.00
chip_sw_i2c_host_tx_rx 3 3 100.00
chip_sw_i2c_host_tx_rx 466.830s 5574.157us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 369.820s 4799.011us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 440.660s 4728.859us 1 1 100.00
chip_sw_i2c_device_tx_rx 1 1 100.00
chip_sw_i2c_device_tx_rx 318.240s 3816.561us 1 1 100.00
chip_sw_keymgr_key_derivation 2 2 100.00
chip_sw_keymgr_key_derivation 589.270s 6310.391us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1644.150s 13340.390us 1 1 100.00
chip_sw_keymgr_sideload_kmac 1 1 100.00
chip_sw_keymgr_sideload_kmac 1314.220s 9836.573us 1 1 100.00
chip_sw_keymgr_sideload_aes 1 1 100.00
chip_sw_keymgr_sideload_aes 741.130s 8292.070us 1 1 100.00
chip_sw_keymgr_sideload_otbn 1 1 100.00
chip_sw_keymgr_sideload_otbn 1928.820s 9913.380us 1 1 100.00
chip_sw_kmac_enc 3 3 100.00
chip_sw_kmac_mode_cshake 150.080s 2583.495us 1 1 100.00
chip_sw_kmac_mode_kmac 218.500s 3169.960us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 149.940s 2575.583us 1 1 100.00
chip_sw_kmac_app_keymgr 1 1 100.00
chip_sw_keymgr_key_derivation 589.270s 6310.391us 1 1 100.00
chip_sw_kmac_app_lc 1 1 100.00
chip_sw_lc_ctrl_transition 654.050s 11970.098us 1 1 100.00
chip_sw_kmac_app_rom 1 1 100.00
chip_sw_kmac_app_rom 146.200s 2484.525us 1 1 100.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 949.100s 7216.198us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 180.610s 3605.792us 1 1 100.00
chip_sw_lc_ctrl_alert_handler_escalation 1 1 100.00
chip_sw_alert_handler_escalation 309.600s 5046.108us 1 1 100.00
chip_sw_lc_ctrl_jtag_access 3 3 100.00
chip_tap_straps_dev 912.150s 15285.479us 1 1 100.00
chip_tap_straps_rma 343.230s 5749.134us 1 1 100.00
chip_tap_straps_prod 85.820s 2337.577us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 186.670s 2743.401us 1 1 100.00
chip_sw_lc_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 654.050s 11970.098us 1 1 100.00
chip_sw_lc_ctrl_transitions 1 1 100.00
chip_sw_lc_ctrl_transition 654.050s 11970.098us 1 1 100.00
chip_sw_lc_ctrl_kmac_req 1 1 100.00
chip_sw_lc_ctrl_transition 654.050s 11970.098us 1 1 100.00
chip_sw_lc_ctrl_key_div 1 1 100.00
chip_sw_keymgr_key_derivation_prod 1159.150s 8702.504us 1 1 100.00
chip_sw_lc_ctrl_broadcast 20 22 90.91
chip_sw_flash_ctrl_lc_rw_en 132.520s 3168.919us 0 1 0.00
chip_sw_flash_rma_unlocked 3495.010s 43586.070us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 206.760s 3213.104us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 470.130s 6755.898us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 562.710s 6465.284us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 500.860s 5854.352us 0 1 0.00
chip_sw_lc_ctrl_transition 654.050s 11970.098us 1 1 100.00
chip_sw_keymgr_key_derivation 589.270s 6310.391us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 357.980s 8628.935us 1 1 100.00
chip_sw_sram_ctrl_execution_main 624.990s 8794.979us 1 1 100.00
chip_prim_tl_access 461.480s 13631.693us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 697.140s 12509.834us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 381.670s 4291.024us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 378.130s 4972.678us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 387.610s 4139.847us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 409.600s 4946.073us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 371.710s 3900.569us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 360.400s 4580.175us 1 1 100.00
chip_tap_straps_dev 912.150s 15285.479us 1 1 100.00
chip_tap_straps_rma 343.230s 5749.134us 1 1 100.00
chip_tap_straps_prod 85.820s 2337.577us 1 1 100.00
chip_rv_dm_lc_disabled 289.170s 13925.824us 1 1 100.00
chip_lc_scrap 4 4 100.00
chip_sw_lc_ctrl_rma_to_scrap 167.990s 3779.990us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 95.470s 2739.902us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 96.620s 3027.635us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 186.750s 3367.905us 1 1 100.00
chip_lc_test_locked 2 2 100.00
chip_sw_lc_walkthrough_testunlocks 1868.970s 36523.802us 1 1 100.00
chip_rv_dm_lc_disabled 289.170s 13925.824us 1 1 100.00
chip_sw_lc_walkthrough 2 5 40.00
chip_sw_lc_walkthrough_dev 567.170s 11497.882us 0 1 0.00
chip_sw_lc_walkthrough_prod 546.460s 9501.868us 0 1 0.00
chip_sw_lc_walkthrough_prodend 507.120s 9879.870us 1 1 100.00
chip_sw_lc_walkthrough_rma 315.040s 6325.616us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 1868.970s 36523.802us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 2 3 66.67
chip_sw_lc_ctrl_volatile_raw_unlock 70.700s 2593.638us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 68.130s 2567.060us 1 1 100.00
rom_volatile_raw_unlock 36.029s 0.000us 0 1 0.00
chip_sw_otbn_op 2 2 100.00
chip_sw_otbn_ecdsa_op_irq 3788.520s 17270.526us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3670.220s 19526.534us 1 1 100.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 562.190s 5713.271us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 562.190s 5713.271us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 562.190s 5713.271us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 258.210s 3403.361us 1 1 100.00
chip_otp_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 654.050s 11970.098us 1 1 100.00
chip_sw_otp_ctrl_keys 5 5 100.00
chip_sw_flash_init 1413.360s 22195.852us 1 1 100.00
chip_sw_otbn_mem_scramble 258.210s 3403.361us 1 1 100.00
chip_sw_keymgr_key_derivation 589.270s 6310.391us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 327.880s 4968.506us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 146.700s 2715.063us 1 1 100.00
chip_sw_otp_ctrl_entropy 5 5 100.00
chip_sw_flash_init 1413.360s 22195.852us 1 1 100.00
chip_sw_otbn_mem_scramble 258.210s 3403.361us 1 1 100.00
chip_sw_keymgr_key_derivation 589.270s 6310.391us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 327.880s 4968.506us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 146.700s 2715.063us 1 1 100.00
chip_sw_otp_ctrl_program 1 1 100.00
chip_sw_lc_ctrl_transition 654.050s 11970.098us 1 1 100.00
chip_sw_otp_ctrl_program_error 1 1 100.00
chip_sw_lc_ctrl_program_error 387.250s 5266.183us 1 1 100.00
chip_sw_otp_ctrl_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 186.670s 2743.401us 1 1 100.00
chip_sw_otp_ctrl_lc_signals 5 6 83.33
chip_sw_otp_ctrl_lc_signals_test_unlocked0 206.760s 3213.104us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 470.130s 6755.898us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 562.710s 6465.284us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 500.860s 5854.352us 0 1 0.00
chip_sw_lc_ctrl_transition 654.050s 11970.098us 1 1 100.00
chip_prim_tl_access 461.480s 13631.693us 1 1 100.00
chip_sw_otp_prim_tl_access 1 1 100.00
chip_prim_tl_access 461.480s 13631.693us 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 907.490s 7086.130us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 60.480s 2130.710us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1200.100s 28162.266us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 205.640s 7618.926us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 434.010s 7580.470us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 444.900s 7729.799us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1172.830s 25289.804us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 1 2 50.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 366.450s 9292.271us 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 492.900s 7812.034us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 788.150s 9962.845us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 1 1 100.00
chip_sw_pwrmgr_wdog_reset 293.330s 3855.214us 1 1 100.00
chip_sw_pwrmgr_aon_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 60.480s 2130.710us 0 1 0.00
chip_sw_pwrmgr_main_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 265.110s 4468.312us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 236.510s 4875.243us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 365.150s 8428.676us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_sleep_power_glitch_reset 172.190s 3740.812us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1501.470s 21108.492us 1 1 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 752.150s 8734.051us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1041.360s 12554.093us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1695.210s 32283.659us 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 179.650s 3059.847us 1 1 100.00
chip_sw_pwrmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 416.890s 5504.898us 1 1 100.00
chip_sw_rom_access 1 1 100.00
chip_sw_rom_ctrl_integrity_check 357.980s 8628.935us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 1 1 100.00
chip_sw_rom_ctrl_integrity_check 357.980s 8628.935us 1 1 100.00
chip_sw_rstmgr_non_sys_reset_info 4 4 100.00
chip_sw_pwrmgr_all_reset_reqs 1041.360s 12554.093us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1501.470s 21108.492us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 293.330s 3855.214us 1 1 100.00
chip_sw_pwrmgr_smoketest 305.160s 5588.296us 1 1 100.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 211.130s 3353.597us 1 1 100.00
chip_sw_rstmgr_cpu_info 1 1 100.00
chip_sw_rstmgr_cpu_info 471.040s 6956.851us 1 1 100.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 246.940s 4185.563us 1 1 100.00
chip_sw_rstmgr_alert_info 1 1 100.00
chip_sw_rstmgr_alert_info 1042.900s 10445.407us 1 1 100.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 187.580s 3618.572us 1 1 100.00
chip_sw_rstmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 416.890s 5504.898us 1 1 100.00
chip_sw_rstmgr_alert_handler_reset_enables 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1069.810s 8614.901us 1 1 100.00
chip_sw_nmi_irq 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 487.370s 4667.684us 1 1 100.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 475.550s 4546.607us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 183.770s 3126.545us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 146.700s 2715.063us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 1 1 100.00
chip_sw_rstmgr_cpu_info 471.040s 6956.851us 1 1 100.00
chip_sw_rv_core_ibex_double_fault 1 1 100.00
chip_sw_rstmgr_cpu_info 471.040s 6956.851us 1 1 100.00
chip_jtag_csr_rw 1 1 100.00
chip_jtag_csr_rw 1595.070s 20172.661us 1 1 100.00
chip_jtag_mem_access 1 1 100.00
chip_jtag_mem_access 922.870s 13632.834us 1 1 100.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 211.130s 3353.597us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 173.880s 2767.961us 0 1 0.00
chip_rv_dm_access_after_wakeup 1 1 100.00
chip_sw_rv_dm_access_after_wakeup 294.470s 5312.328us 1 1 100.00
chip_sw_rv_dm_jtag_tap_sel 1 1 100.00
chip_tap_straps_rma 343.230s 5749.134us 1 1 100.00
chip_rv_dm_lc_disabled 1 1 100.00
chip_rv_dm_lc_disabled 289.170s 13925.824us 1 1 100.00
chip_sw_plic_all_irqs 3 3 100.00
chip_plic_all_irqs_0 574.910s 5177.612us 1 1 100.00
chip_plic_all_irqs_10 231.530s 3338.079us 1 1 100.00
chip_plic_all_irqs_20 396.950s 3858.410us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 169.280s 2607.927us 1 1 100.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 161.220s 2913.772us 1 1 100.00
chip_sw_spi_device_flash_mode 1 1 100.00
rom_e2e_smoke 2955.650s 15307.613us 1 1 100.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 455.910s 7218.662us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 181.810s 3546.353us 0 1 0.00
chip_sw_spi_device_tpm 1 1 100.00
chip_sw_spi_device_tpm 223.270s 3480.581us 1 1 100.00
chip_sw_spi_host_tx_rx 1 1 100.00
chip_sw_spi_host_tx_rx 201.190s 3359.408us 1 1 100.00
chip_sw_sram_scrambled_access 2 2 100.00
chip_sw_sram_ctrl_scrambled_access 327.880s 4968.506us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 393.530s 5671.581us 1 1 100.00
chip_sw_sleep_sram_ret_contents 2 2 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 373.590s 7593.522us 1 1 100.00
chip_sw_sleep_sram_ret_contents_scramble 424.560s 8309.596us 1 1 100.00
chip_sw_sram_execution 1 1 100.00
chip_sw_sram_ctrl_execution_main 624.990s 8794.979us 1 1 100.00
chip_sw_sram_lc_escalation 2 2 100.00
chip_sw_all_escalation_resets 416.890s 5504.898us 1 1 100.00
chip_sw_data_integrity_escalation 414.840s 5891.805us 1 1 100.00
chip_sw_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 752.150s 8734.051us 1 1 100.00
chip_sw_sysrst_ctrl_reset 971.440s 22011.723us 1 1 100.00
chip_sw_sysrst_ctrl_inputs 1 1 100.00
chip_sw_sysrst_ctrl_inputs 148.230s 2689.028us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 1 1 100.00
chip_sw_sysrst_ctrl_outputs 214.170s 4051.191us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 326.650s 4129.636us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 1 1 100.00
chip_sw_sysrst_ctrl_reset 971.440s 22011.723us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_reset 1 1 100.00
chip_sw_sysrst_ctrl_reset 971.440s 22011.723us 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2515.790s 20228.021us 1 1 100.00
chip_sw_sysrst_ctrl_flash_wp_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2515.790s 20228.021us 1 1 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 1 2 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 366.530s 6588.765us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3058.740s 34539.327us 0 1 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 170.780s 2884.359us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 131.840s 2898.902us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 260.660s 3576.512us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 335.270s 3813.189us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 986.800s 8554.651us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 4842.580s 31774.874us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 1715.250s 11936.551us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 133.330s 2882.315us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 220.140s 3108.679us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 67.280s 2392.621us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 10200.860s 71574.801us 1 1 100.00
chip_sw_power_max_load 1 1 100.00
chip_sw_power_virus 1121.930s 6890.171us 1 1 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 168.690s 4394.741us 0 1 0.00
rom_e2e_jtag_debug_dev 150.600s 3552.665us 0 1 0.00
rom_e2e_jtag_debug_rma 394.610s 7765.083us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 215.580s 4126.789us 0 1 0.00
rom_e2e_jtag_inject_dev 79.880s 2650.987us 0 1 0.00
rom_e2e_jtag_inject_rma 65.250s 2861.807us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 128.818s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 1 0.00
chip_sw_clkmgr_jitter_frequency 302.110s 3832.270us 0 1 0.00
chip_sw_edn_boot_mode 1 1 100.00
chip_sw_edn_boot_mode 320.020s 3252.501us 1 1 100.00
chip_sw_edn_auto_mode 1 1 100.00
chip_sw_edn_auto_mode 661.440s 4812.952us 1 1 100.00
chip_sw_edn_sw_mode 1 1 100.00
chip_sw_edn_sw_mode 947.750s 8119.126us 1 1 100.00
chip_sw_edn_kat 1 1 100.00
chip_sw_edn_kat 250.980s 2459.782us 1 1 100.00
chip_sw_flash_memory_protection 1 1 100.00
chip_sw_flash_ctrl_mem_protection 627.200s 5587.698us 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 136.770s 2795.629us 1 1 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 176.720s 3299.704us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 1 1 100.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 317.160s 5778.628us 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 299.480s 4092.499us 1 1 100.00
chip_sw_all_resets 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1041.360s 12554.093us 1 1 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 168.690s 4394.741us 0 1 0.00
rom_e2e_jtag_debug_dev 150.600s 3552.665us 0 1 0.00
rom_e2e_jtag_debug_rma 394.610s 7765.083us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 1 1 100.00
chip_sw_rv_dm_access_after_escalation_reset 416.310s 5749.420us 1 1 100.00
chip_sw_plic_alerts 1 1 100.00
chip_sw_all_escalation_resets 416.890s 5504.898us 1 1 100.00
tick_configuration 1 1 100.00
chip_sw_rv_timer_systick_test 5687.400s 38490.582us 1 1 100.00
counter_wrap 1 1 100.00
chip_sw_rv_timer_systick_test 5687.400s 38490.582us 1 1 100.00
chip_sw_spi_device_output_when_disabled_or_sleeping 1 1 100.00
chip_sw_spi_device_pinmux_sleep_retention 178.450s 3838.332us 1 1 100.00
chip_sw_uart_watermarks 1 1 100.00
chip_sw_uart_tx_rx 345.720s 5155.792us 1 1 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 2765.490s 18850.438us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 8 10 80.00
chip_sival_flash_info_access 212.190s 3047.546us 1 1 100.00
chip_sw_rstmgr_rst_cnsty_escalation 425.680s 5502.524us 1 1 100.00
chip_sw_otp_ctrl_rot_auth_config 4.620s 0.000us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 155.770s 2565.040us 1 1 100.00
chip_sw_otp_ctrl_descrambling 166.040s 2645.359us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 246.820s 3898.396us 1 1 100.00
chip_sw_pwrmgr_sleep_wake_5_bug 8.417s 0.000us 0 1 0.00
chip_sw_flash_ctrl_write_clear 245.080s 3662.317us 1 1 100.00
ate_bootstrap_flash_erase 6534.420s 45026.678us 1 1 100.00
ate_bootstrap_disjoint 9711.270s 84733.924us 1 1 100.00

Error Messages

   Test seed line log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 24 test runs
chip_sw_pwrmgr_sleep_wake_5_bug 17946463652713697037237413979156372651498506954599561868410459342058399370953 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 50122941984582861832274773305122800913866006834360987245145825276644746810747 None
Another command (pid=395095) is running. Waiting for it to complete on the server (server_pid=274897)...
Another command (pid=413755) is running. Waiting for it to complete on the server (server_pid=274897)...
Another command (pid=432691) is running. Waiting for it to complete on the server (server_pid=274897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_dev 62482109572671310625418834030854134671175055977043148865359072467762517331029 None
---- STDERR ----
Another command (pid=375873) is running. Waiting for it to complete on the server (server_pid=274897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod 95316200884027736308370685061533790811204876491333917595243385956047709408630 None
---- STDERR ----
Another command (pid=441008) is running. Waiting for it to complete on the server (server_pid=274897)...
Another command (pid=439515) is running. Waiting for it to complete on the server (server_pid=274897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 84704068413582512516523142544377434974206925893147608802759522621142027315344 None
Another command (pid=447913) is running. Waiting for it to complete on the server (server_pid=274897)...
Another command (pid=559032) is running. Waiting for it to complete on the server (server_pid=274897)...
Another command (pid=565307) is running. Waiting for it to complete on the server (server_pid=274897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_rma 17743145138419840832265665046878474437160040899220703994769360566003444872499 None
Another command (pid=532650) is running. Waiting for it to complete on the server (server_pid=274897)...
Another command (pid=440377) is running. Waiting for it to complete on the server (server_pid=274897)...
Another command (pid=447913) is running. Waiting for it to complete on the server (server_pid=274897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 2324440802116540543925913048777985734665972486902818481436236944873748547051 None
Another command (pid=361531) is running. Waiting for it to complete on the server (server_pid=274897)...
Another command (pid=413755) is running. Waiting for it to complete on the server (server_pid=274897)...
Another command (pid=359290) is running. Waiting for it to complete on the server (server_pid=274897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_dev 14046076748407683631788496321741243663268409545118379888218038022995324334101 None
Another command (pid=578172) is running. Waiting for it to complete on the server (server_pid=274897)...
Another command (pid=651584) is running. Waiting for it to complete on the server (server_pid=274897)...
Another command (pid=660934) is running. Waiting for it to complete on the server (server_pid=274897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod 86100979896933905156947689558342725482768563766898080632672047193823681428474 None
Another command (pid=629157) is running. Waiting for it to complete on the server (server_pid=274897)...
Another command (pid=655055) is running. Waiting for it to complete on the server (server_pid=274897)...
Another command (pid=653288) is running. Waiting for it to complete on the server (server_pid=274897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 60229210736781191394520379860648751130423008151235011981060350995630110877597 None
Another command (pid=580774) is running. Waiting for it to complete on the server (server_pid=274897)...
Another command (pid=392447) is running. Waiting for it to complete on the server (server_pid=274897)...
Another command (pid=568628) is running. Waiting for it to complete on the server (server_pid=274897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_rma 52708019507803531385919416489883337913884882978743809757949674675594839274675 None
---- STDERR ----
Another command (pid=435926) is running. Waiting for it to complete on the server (server_pid=274897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 14544049354991221081926169860074719363898439897181256087640147482230375572329 None
---- STDERR ----
Another command (pid=441463) is running. Waiting for it to complete on the server (server_pid=274897)...
Another command (pid=476023) is running. Waiting for it to complete on the server (server_pid=274897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_dev 106451694054356379460214512055791153914651733021421167973042259086944922202407 None
Another command (pid=580774) is running. Waiting for it to complete on the server (server_pid=274897)...
Another command (pid=392447) is running. Waiting for it to complete on the server (server_pid=274897)...
Another command (pid=568628) is running. Waiting for it to complete on the server (server_pid=274897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod 65657717300736173152867601850278443953560954763209694161967229143091979876888 None
Another command (pid=535265) is running. Waiting for it to complete on the server (server_pid=274897)...
Another command (pid=454207) is running. Waiting for it to complete on the server (server_pid=274897)...
Another command (pid=428860) is running. Waiting for it to complete on the server (server_pid=274897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 15482637313213995839542654212557922284553723848925934131491192918287938756212 None
Another command (pid=441008) is running. Waiting for it to complete on the server (server_pid=274897)...
Another command (pid=439515) is running. Waiting for it to complete on the server (server_pid=274897)...
Another command (pid=532650) is running. Waiting for it to complete on the server (server_pid=274897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_rma 45053907853693144393288714724397578216345458145270174726632416381059462475814 None
Another command (pid=559032) is running. Waiting for it to complete on the server (server_pid=274897)...
Another command (pid=565307) is running. Waiting for it to complete on the server (server_pid=274897)...
Another command (pid=562251) is running. Waiting for it to complete on the server (server_pid=274897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_test_unlocked0 114964817555774069772143651276727906330120426622886688431982758339365312956885 None
Another command (pid=361531) is running. Waiting for it to complete on the server (server_pid=274897)...
Another command (pid=413755) is running. Waiting for it to complete on the server (server_pid=274897)...
Another command (pid=432691) is running. Waiting for it to complete on the server (server_pid=274897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_dev 26412893800451081292840821915091444128601247191388676412929441546843616734842 None
Another command (pid=535265) is running. Waiting for it to complete on the server (server_pid=274897)...
Another command (pid=428860) is running. Waiting for it to complete on the server (server_pid=274897)...
Another command (pid=503989) is running. Waiting for it to complete on the server (server_pid=274897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod 62969529833068859837748429784537093583002271246696763021590959675228469730326 None
Another command (pid=573603) is running. Waiting for it to complete on the server (server_pid=274897)...
Another command (pid=604741) is running. Waiting for it to complete on the server (server_pid=274897)...
Another command (pid=579687) is running. Waiting for it to complete on the server (server_pid=274897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod_end 5429828538028407943604601315050456185545700134965715158469135265615405674815 None
---- STDERR ----
Another command (pid=440032) is running. Waiting for it to complete on the server (server_pid=274897)...
Another command (pid=442384) is running. Waiting for it to complete on the server (server_pid=274897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_rma 12771042704529804827694815661213844687588532020922694810721920116609480246631 None
Another command (pid=441463) is running. Waiting for it to complete on the server (server_pid=274897)...
Another command (pid=476023) is running. Waiting for it to complete on the server (server_pid=274897)...
Another command (pid=535265) is running. Waiting for it to complete on the server (server_pid=274897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_volatile_raw_unlock 66533412070934119753886793317033849794346203849698066945288638365338710527807 None
Another command (pid=359288) is running. Waiting for it to complete on the server (server_pid=274897)...
Another command (pid=361531) is running. Waiting for it to complete on the server (server_pid=274897)...
Another command (pid=413755) is running. Waiting for it to complete on the server (server_pid=274897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_raw_unlock 58073137161146603384598830513518676362988136677425726143203461604066450474794 None
---- STDERR ----
Another command (pid=359288) is running. Waiting for it to complete on the server (server_pid=274897)...
Another command (pid=361531) is running. Waiting for it to complete on the server (server_pid=274897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 54892702647504394480644884505072537701963271501404430433860316035785344065769 None
Another command (pid=570145) is running. Waiting for it to complete on the server (server_pid=274897)...
Another command (pid=454746) is running. Waiting for it to complete on the server (server_pid=274897)...
Another command (pid=580774) is running. Waiting for it to complete on the server (server_pid=274897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Error-[NOA] Null object access 7 test runs
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 19278661890316963873881540422757547628703579238121236986155418938147273261658 327
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_test_unlocked0 19421616152647673269885459551076979266495259270702619124280241438986011960578 319
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_dev 29254207468320758137603444476237951505345014910135947886350651523072681185633 319
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_rma 82274966596863067385743992274231053031294589306586679218645566058204076432205 352
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 32627678709055390961456963013752632752119583867664247787815209500518746313951 310
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 44277648518509597992675422856672765603764771290937165641356631818049958032185 305
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 60820469866788419172004892814194994883864423878945992892746439758607017265609 303
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode 6 test runs
rom_e2e_sigverify_always_a_bad_b_bad_prod 32332117939932054715831168472333274762715235218167590658013818201675272003448 365
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 55125305873739633615609064320782287454460922522859321448740444420341886844701 367
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_rma 110344668910663180370560978148259196570845691803949252278110380422490422377097 368
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod 28710939748075500866141412963435710095134245147843645410533164601298168895013 327
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 64151774518685186366205898945177180183653601929293025393279847159899386330189 327
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_rma 70766390552456938230358278989914075349985043407160924470959117103994838223960 325
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 3 test runs
chip_sw_lc_walkthrough_dev 94354553755782812956995420992295461084486470935716816987218938884665597517428 369
UVM_INFO @ 11497.882002 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 9354052100243651112832732287385936491303692188020004906306276966752216441865 369
UVM_INFO @ 9501.868340 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 95137469449095869940279460801893531334948605600202667054852699508752138424928 341
UVM_INFO @ 6325.616278 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode 3 test runs
rom_e2e_sigverify_always_a_nothing_b_bad_prod 71860062841200491677552202635532270493344218946832312646599644088547266572667 328
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 89390765190004443076597225542265615030663874268557047450850874654041408977254 325
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_rma 75198204014739790718895320012501401098725959468208782398645271574426807084235 325
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' 2 test runs
chip_sw_otp_ctrl_escalation 13718091159617173917297239387553920454568918490148529110133787128187669101980 316
UVM_ERROR @ 3299.704408 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3299.704408 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_csrng_fuse_en_sw_app_read_test 111397020419740339087601835088079454768765107512377154006305594149816366682396 312
UVM_ERROR @ 2901.381264 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2901.381264 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))' 2 test runs
chip_sw_pwrmgr_sleep_power_glitch_reset 72874266175336467136577071209681428145401879690771664212109131051349052886003 313
UVM_ERROR @ 3740.811930 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 3740.811930 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 102827137052861571590798162899597897430501607919582175768044717197103883417960 315
UVM_ERROR @ 4875.243167 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 4875.243167 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *). 2 test runs
chip_tl_errors 8452444293518899336868395562680719525099678863756821608008813611345414543721 217
TL item was: req: (cip_tl_seq_item@33831) { a_addr: 'h10544 a_data: 'h9537bd6d a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h29 a_opcode: 'h4 a_user: 'h1b6d2 d_param: 'h0 d_source: 'h29 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2432.247008 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 39164371416830772020445874196795766982482970713801349775288136453446236921259 224
TL item was: req: (cip_tl_seq_item@31765) { a_addr: 'h107e0 a_data: 'he5a2a422 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h19941 d_param: 'h0 d_source: 'h0 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2238.729829 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode 2 test runs
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 69522075484252481649756320036786823508835941413692379253414621258808350937404 363
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 78684847581846398478943787123169495764987226504528147636642989856342284575039 325
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode 2 test runs
rom_e2e_sigverify_always_a_bad_b_bad_dev 46962394990869551527491179553559514742763690773094333418345888846774480689227 362
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_dev 5931068267164479320185064694483294739361702342377429793793255822561405597326 327
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$isunknown(pin_wkup_req_o))' 1 test run
chip_sw_sleep_pin_wake 41374462205536880170078947858137225423658924464871844626811304562888283769578 318
UVM_ERROR @ 2857.620000 us: (pinmux.sv:662) [ASSERT FAILED] AonWkupReqKnownO_A
UVM_INFO @ 2857.620000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty 1 test run
chip_sw_spi_device_pass_through_collision 51835269395230807561948221415162799818377126986194747581739196335651972027454 320
UVM_INFO @ 3546.352550 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_flash_ctrl_lc_rw_en 25339130021269798017059393331909465120843967981074615775583638732518208937478 309
UVM_INFO @ 3168.919156 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * 1 test run
chip_sw_otp_ctrl_lc_signals_rma 84755285564180801155449992104372245057099471500313131414643658682689109349114 342
UVM_INFO @ 5854.351570 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode 1 test run
chip_sw_otp_ctrl_rot_auth_config 103672014168480538667877777770168628928219438181617110123648404748178674562582 282
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))' 1 test run
chip_sw_pwrmgr_full_aon_reset 95028681565626846752846455471169226423284821301573915577950965375130239468875 303
UVM_ERROR @ 2130.709590 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 2130.709590 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))' 1 test run
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 39812861092225605261362769614678090266846402857297118643240213639103040562930 327
UVM_ERROR @ 9292.270500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 9292.270500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns 1 test run
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 27266145647322508679360284382767497225057891070808683734383905376340215441011 332
UVM_INFO @ 34539.327392 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! 1 test run
chip_sw_alert_test 54490311399196432213608096245343008169634832304242664188343396134275562311206 307
UVM_INFO @ 3529.108896 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) 1 test run
chip_sw_alert_handler_lpg_sleep_mode_alerts 47342114720961554343727653645239148902237272946336476428626576683413647037658 308
UVM_INFO @ 2891.071304 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
chip_sw_alert_handler_lpg_sleep_mode_pings 38849791380368830756867395364056788260098151063320768884384230348641653303203 None
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_clkmgr_jitter_frequency 19613161321080408165987966619008415454862206390204568393638706367541467736 343
UVM_INFO @ 3832.269645 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * 1 test run
chip_sw_power_idle_load 40389740477666028970808851418725950251014153076387724823474721814410668938066 314
UVM_INFO @ 3389.285000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * 1 test run
chip_sw_power_sleep_load 51671435911116523006783625557206080911618555823688219191784882175650671777174 318
UVM_INFO @ 3738.357000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = * 1 test run
chip_sw_ast_clk_rst_inputs 101927929923210836469593272816007652085181410800816816886061097001861928025882 327
UVM_INFO @ 11149.949044 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode 1 test run
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 64150907218334485505375211491224949197964092440709357281190941232900007472565 325
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode 1 test run
rom_e2e_sigverify_always_a_nothing_b_bad_dev 54237506600353248979778202510253947783915241323320167771141491290294559073386 327
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '$stable(key_data_i)' 1 test run
rom_keymgr_functest 85772309081163703536147458559957913673888149776661175845953813257488672978514 327
UVM_ERROR @ 4968.460706 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 4968.460706 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---