Simulation Results: clkmgr

 
06/05/2026 15:30:23 DVSim: v1.34.0 sha: 238ca4d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.54 %
  • code
  • 98.25 %
  • assert
  • 95.76 %
  • func
  • 86.62 %
  • line
  • 99.00 %
  • branch
  • 98.59 %
  • cond
  • 94.48 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
91.67%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.930s 86.870us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.750s 24.663us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.820s 74.785us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 3.810s 866.313us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 0.970s 66.685us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.150s 41.166us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.820s 74.785us 1 1 100.00
clkmgr_csr_aliasing 0.970s 66.685us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.660s 17.448us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.130s 156.379us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.730s 24.902us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.790s 98.442us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.930s 86.870us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 6.160s 1162.890us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 2.210s 502.758us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 6.160s 1162.890us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 4.500s 1487.298us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.850s 13.862us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.910s 42.696us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.910s 42.696us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.750s 24.663us 1 1 100.00
clkmgr_csr_rw 0.820s 74.785us 1 1 100.00
clkmgr_csr_aliasing 0.970s 66.685us 1 1 100.00
clkmgr_same_csr_outstanding 0.890s 27.808us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.750s 24.663us 1 1 100.00
clkmgr_csr_rw 0.820s 74.785us 1 1 100.00
clkmgr_csr_aliasing 0.970s 66.685us 1 1 100.00
clkmgr_same_csr_outstanding 0.890s 27.808us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 0.760s 16.047us 0 1 0.00
clkmgr_tl_intg_err 1.990s 130.011us 1 1 100.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.750s 151.237us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.750s 151.237us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.750s 151.237us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.750s 151.237us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
clkmgr_shadow_reg_errors_with_csr_rw 1.570s 178.770us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 1.990s 130.011us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 6.160s 1162.890us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 2.210s 502.758us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.750s 151.237us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.880s 80.971us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.780s 60.556us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.790s 62.745us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.750s 21.222us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.750s 24.530us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.820s 74.785us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 0.760s 16.047us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.820s 74.785us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.820s 74.785us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 0.760s 16.047us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 1.630s 317.337us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 79.160s 33272.172us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [clkmgr_common_vseq] expect alert:fatal_fault to fire 1 test run
clkmgr_sec_cm 3048896935793875139525370988580542702245343016423535387198049976886012800999 82
UVM_INFO @ 16047106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---