Simulation Results: edn/edn1

 
06/05/2026 15:30:23 DVSim: v1.34.0 sha: 238ca4d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.42 %
  • code
  • 84.87 %
  • assert
  • 97.14 %
  • func
  • 80.25 %
  • line
  • 98.18 %
  • branch
  • 93.29 %
  • cond
  • 90.54 %
  • toggle
  • 95.76 %
  • FSM
  • 46.59 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.810s 26.009us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.760s 25.019us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.760s 52.348us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.150s 1085.121us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.030s 48.080us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.980s 81.374us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.760s 52.348us 1 1 100.00
edn_csr_aliasing 1.030s 48.080us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.040s 38.952us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.040s 38.952us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.040s 38.952us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.960s 21.180us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.970s 76.293us 1 1 100.00
errs 1 1 100.00
edn_err 0.980s 19.796us 1 1 100.00
disable 2 2 100.00
edn_disable 0.730s 19.638us 1 1 100.00
edn_disable_auto_req_mode 0.860s 36.778us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.720s 1223.061us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.810s 24.197us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.900s 39.373us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.540s 218.277us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.540s 218.277us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.760s 25.019us 1 1 100.00
edn_csr_rw 0.760s 52.348us 1 1 100.00
edn_csr_aliasing 1.030s 48.080us 1 1 100.00
edn_same_csr_outstanding 1.020s 25.913us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.760s 25.019us 1 1 100.00
edn_csr_rw 0.760s 52.348us 1 1 100.00
edn_csr_aliasing 1.030s 48.080us 1 1 100.00
edn_same_csr_outstanding 1.020s 25.913us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 2.150s 1725.472us 1 1 100.00
edn_tl_intg_err 1.370s 91.045us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.890s 18.648us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.970s 76.293us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.150s 1725.472us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.150s 1725.472us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.150s 1725.472us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.150s 1725.472us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.970s 76.293us 1 1 100.00
edn_sec_cm 2.150s 1725.472us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.970s 76.293us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.370s 91.045us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 82.930s 21694.968us 1 1 100.00