Simulation Results: flash_ctrl

 
06/05/2026 15:30:23 DVSim: v1.34.0 sha: 238ca4d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.17 %
  • code
  • 94.58 %
  • assert
  • 95.22 %
  • func
  • 95.70 %
  • line
  • 96.01 %
  • branch
  • 97.12 %
  • cond
  • 93.73 %
  • toggle
  • 98.26 %
  • FSM
  • 87.76 %
Validation stages
V1
100.00%
V2
100.00%
V2S
95.83%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 55.910s 31.228us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 11.560s 29.840us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 13.450s 29.447us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 8.290s 54.159us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 42.810s 2639.129us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 27.330s 3891.215us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 11.230s 185.678us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 8.290s 54.159us 1 1 100.00
flash_ctrl_csr_aliasing 27.330s 3891.215us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 10.730s 20.523us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 7.360s 43.351us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 13.250s 25.788us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 31.650s 166.442us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1267.810s 334812.353us 1 1 100.00
flash_ctrl_hw_rma_reset 541.190s 160184.652us 1 1 100.00
flash_ctrl_lcmgr_intg 7.060s 22.851us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1207.510s 260910.586us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 281.970s 8171.533us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 5.500s 34.110us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 1847.630s 91905.695us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 76.510s 735.966us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 28.240s 50.933us 1 1 100.00
flash_ctrl_rw_evict_all_en 14.360s 32.015us 1 1 100.00
flash_ctrl_re_evict 16.520s 64.374us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 24.590s 33.012us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 24.590s 33.012us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 127.200s 20930.995us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 12.330s 241.376us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 451.200s 321.830us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 394.100s 70739.880us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 321.240s 330.440us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 1010.000s 2725.177us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 5.730s 42.545us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 136.240s 2355.365us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 13.480s 32.270us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 6.700s 19.402us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 429.630s 956.036us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 86.630s 10999.888us 1 1 100.00
flash_ctrl_otp_reset 52.440s 38.080us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1267.810s 334812.353us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 198.760s 7223.104us 1 1 100.00
flash_ctrl_intr_wr 73.110s 21821.819us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 179.680s 12753.945us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 150.430s 153145.909us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 57.970s 3489.515us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 41.320s 2663.003us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 10.600s 71.187us 1 1 100.00
flash_ctrl_ro_derr 109.440s 1567.145us 1 1 100.00
flash_ctrl_rw_derr 144.430s 1769.922us 1 1 100.00
flash_ctrl_derr_detect 120.250s 824.742us 1 1 100.00
flash_ctrl_integrity 342.170s 3144.530us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 13.320s 93.243us 1 1 100.00
flash_ctrl_ro_serr 91.380s 614.116us 1 1 100.00
flash_ctrl_rw_serr 167.520s 1871.987us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 53.050s 2789.930us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 63.890s 1919.560us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 144.570s 2757.699us 1 1 100.00
flash_ctrl_write_word_sweep 6.990s 186.734us 1 1 100.00
flash_ctrl_read_word_sweep 6.830s 56.594us 1 1 100.00
flash_ctrl_ro 92.680s 2643.658us 1 1 100.00
flash_ctrl_rw 473.200s 9078.331us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 27.620s 706.686us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 650.840s 157506.174us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 50.650s 10088.726us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 5.670s 27.615us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 7.590s 98.334us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 10.560s 459.722us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 10.560s 459.722us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 13.450s 29.447us 1 1 100.00
flash_ctrl_csr_rw 8.290s 54.159us 1 1 100.00
flash_ctrl_csr_aliasing 27.330s 3891.215us 1 1 100.00
flash_ctrl_same_csr_outstanding 9.720s 172.550us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 13.450s 29.447us 1 1 100.00
flash_ctrl_csr_rw 8.290s 54.159us 1 1 100.00
flash_ctrl_csr_aliasing 27.330s 3891.215us 1 1 100.00
flash_ctrl_same_csr_outstanding 9.720s 172.550us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 31.650s 144.544us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 31.650s 144.544us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 31.650s 144.544us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 31.650s 144.544us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 44.110s 1014.755us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_sec_cm 1534.070s 3408.247us 1 1 100.00
flash_ctrl_tl_intg_err 181.820s 1679.347us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 181.820s 1679.347us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 181.820s 1679.347us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 15.360s 68.136us 1 1 100.00
flash_ctrl_wr_intg 6.640s 89.500us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 55.910s 31.228us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 52.440s 38.080us 1 1 100.00
flash_ctrl_disable 13.480s 32.270us 1 1 100.00
flash_ctrl_sec_info_access 43.160s 4017.781us 1 1 100.00
flash_ctrl_connect 6.700s 19.402us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 5.360s 27.750us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.290s 54.159us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 31.650s 144.544us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.290s 54.159us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 31.650s 144.544us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.290s 54.159us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 31.650s 144.544us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 13.480s 32.270us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 15.360s 68.136us 1 1 100.00
flash_ctrl_access_after_disable 5.720s 20.448us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 13.480s 64.832us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 13.480s 32.270us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 12.330s 241.376us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 473.200s 9078.331us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 167.520s 1871.987us 1 1 100.00
flash_ctrl_rw_derr 144.430s 1769.922us 1 1 100.00
flash_ctrl_integrity 342.170s 3144.530us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1267.810s 334812.353us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1534.070s 3408.247us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1534.070s 3408.247us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1534.070s 3408.247us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1534.070s 3408.247us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 8.810s 762.217us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 0 1 0.00
flash_ctrl_phy_host_grant_err 7.800s 24.901us 0 1 0.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 6.410s 141.341us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1534.070s 3408.247us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1534.070s 3408.247us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1534.070s 3408.247us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 18.450s 50.727us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 382.330s 975.022us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert fatal_err did not trigger max_delay:* 1 test run
flash_ctrl_phy_host_grant_err 75886853851862757326263125420849996002582658455510185138009118450144068982733 123
UVM_INFO @ 24901.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---