Simulation Results: hmac

 
06/05/2026 15:30:23 DVSim: v1.34.0 sha: 238ca4d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.04 %
  • code
  • 97.92 %
  • assert
  • 96.70 %
  • func
  • 42.51 %
  • line
  • 99.64 %
  • branch
  • 99.34 %
  • cond
  • 96.51 %
  • toggle
  • 100.00 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 2.770s 507.241us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.790s 46.377us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.790s 18.209us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 3.910s 114.994us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 2.520s 3036.264us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.830s 104.200us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.790s 18.209us 1 1 100.00
hmac_csr_aliasing 2.520s 3036.264us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 9.470s 683.218us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 47.020s 8720.643us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 188.520s 24806.338us 1 1 100.00
hmac_test_sha384_vectors 19.460s 643.006us 1 1 100.00
hmac_test_sha512_vectors 20.320s 3940.169us 1 1 100.00
hmac_test_hmac256_vectors 6.660s 989.942us 1 1 100.00
hmac_test_hmac384_vectors 7.300s 436.265us 1 1 100.00
hmac_test_hmac512_vectors 6.990s 640.780us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 7.680s 11023.055us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 83.310s 769.441us 1 1 100.00
error 1 1 100.00
hmac_error 15.140s 3652.671us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 38.890s 8388.462us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 2.770s 507.241us 1 1 100.00
hmac_long_msg 9.470s 683.218us 1 1 100.00
hmac_back_pressure 47.020s 8720.643us 1 1 100.00
hmac_datapath_stress 83.310s 769.441us 1 1 100.00
hmac_burst_wr 7.680s 11023.055us 1 1 100.00
hmac_stress_all 345.670s 150199.315us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 2.770s 507.241us 1 1 100.00
hmac_long_msg 9.470s 683.218us 1 1 100.00
hmac_back_pressure 47.020s 8720.643us 1 1 100.00
hmac_datapath_stress 83.310s 769.441us 1 1 100.00
hmac_wipe_secret 38.890s 8388.462us 1 1 100.00
hmac_test_sha256_vectors 188.520s 24806.338us 1 1 100.00
hmac_test_sha384_vectors 19.460s 643.006us 1 1 100.00
hmac_test_sha512_vectors 20.320s 3940.169us 1 1 100.00
hmac_test_hmac256_vectors 6.660s 989.942us 1 1 100.00
hmac_test_hmac384_vectors 7.300s 436.265us 1 1 100.00
hmac_test_hmac512_vectors 6.990s 640.780us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 2.770s 507.241us 1 1 100.00
hmac_long_msg 9.470s 683.218us 1 1 100.00
hmac_back_pressure 47.020s 8720.643us 1 1 100.00
hmac_datapath_stress 83.310s 769.441us 1 1 100.00
hmac_burst_wr 7.680s 11023.055us 1 1 100.00
hmac_error 15.140s 3652.671us 1 1 100.00
hmac_wipe_secret 38.890s 8388.462us 1 1 100.00
hmac_test_sha256_vectors 188.520s 24806.338us 1 1 100.00
hmac_test_sha384_vectors 19.460s 643.006us 1 1 100.00
hmac_test_sha512_vectors 20.320s 3940.169us 1 1 100.00
hmac_test_hmac256_vectors 6.660s 989.942us 1 1 100.00
hmac_test_hmac384_vectors 7.300s 436.265us 1 1 100.00
hmac_test_hmac512_vectors 6.990s 640.780us 1 1 100.00
hmac_stress_all 345.670s 150199.315us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 345.670s 150199.315us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.650s 14.890us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.600s 12.156us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 4.390s 249.772us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 4.390s 249.772us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.790s 46.377us 1 1 100.00
hmac_csr_rw 0.790s 18.209us 1 1 100.00
hmac_csr_aliasing 2.520s 3036.264us 1 1 100.00
hmac_same_csr_outstanding 1.020s 640.161us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.790s 46.377us 1 1 100.00
hmac_csr_rw 0.790s 18.209us 1 1 100.00
hmac_csr_aliasing 2.520s 3036.264us 1 1 100.00
hmac_same_csr_outstanding 1.020s 640.161us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.060s 86.521us 1 1 100.00
hmac_tl_intg_err 1.450s 202.648us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 1.450s 202.648us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 2.770s 507.241us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 3.060s 138.551us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 195.100s 17019.500us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.180s 146.892us 1 1 100.00