Simulation Results

Simulation Results: i2c

06/05/2026 15:30:23 DVSim: v1.34.0 sha: 238ca4d json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
86.30 %

code
81.62 %

assert
96.19 %

func
81.08 %

line
96.41 %

branch
92.33 %

cond
85.04 %

toggle
89.66 %

FSM
44.64 %

Validation stages

V1		100.00%
V2		90.24%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	17.890s	9922.036us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	14.990s	2790.611us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.750s	238.011us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.710s	24.121us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	3.590s	1122.569us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.200s	55.148us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	0.720s	24.954us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.710s	24.121us	1	1	100.00
	i2c_csr_aliasing	1.200s	55.148us	1	1	100.00

37/41 passed

90.24 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	0.920s	36.515us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	318.550s	38114.385us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	67.670s	12422.937us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.920s	16.525us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	40.870s	3090.693us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	121.000s	10025.323us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	1.320s	511.010us	1	1	100.00
	i2c_host_fifo_fmt_empty	13.500s	394.430us	1	1	100.00
	i2c_host_fifo_reset_rx	2.190s	164.881us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	35.190s	7735.292us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	6.720s	553.986us	1	1	100.00
i2c_host_mode_toggle				1	1	100.00
	i2c_host_mode_toggle	4.350s	174.225us	1	1	100.00
target_glitch				0	1	0.00
	i2c_target_glitch	2.360s	2083.435us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	179.880s	42794.913us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	4.160s	3023.460us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	5.040s	1495.338us	1	1	100.00
	i2c_target_intr_smoke	3.440s	2831.059us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	1.760s	381.227us	1	1	100.00
	i2c_target_fifo_reset_tx	1.310s	249.700us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	8.990s	18866.401us	1	1	100.00
	i2c_target_stress_rd	5.040s	1495.338us	1	1	100.00
	i2c_target_intr_stress_wr	114.700s	25420.496us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	5.170s	1143.705us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	1.120s	166.208us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	4.930s	1297.780us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	3.060s	11422.853us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	1.000s	69.492us	1	1	100.00
	i2c_target_fifo_watermarks_tx	1.240s	78.955us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	67.670s	12422.937us	1	1	100.00
	i2c_host_perf_precise	110.520s	24462.672us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	6.720s	553.986us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	2.710s	204.199us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	2.870s	5300.765us	1	1	100.00
	i2c_target_nack_acqfull_addr	1.860s	993.933us	1	1	100.00
	i2c_target_nack_txstretch	1.400s	174.851us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	2.870s	446.262us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	1.820s	1001.467us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.750s	23.442us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.760s	39.505us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	1.420s	56.996us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	1.420s	56.996us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.750s	238.011us	1	1	100.00
	i2c_csr_rw	0.710s	24.121us	1	1	100.00
	i2c_csr_aliasing	1.200s	55.148us	1	1	100.00
	i2c_same_csr_outstanding	1.250s	59.292us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.750s	238.011us	1	1	100.00
	i2c_csr_rw	0.710s	24.121us	1	1	100.00
	i2c_csr_aliasing	1.200s	55.148us	1	1	100.00
	i2c_same_csr_outstanding	1.250s	59.292us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	2.130s	238.634us	1	1	100.00
	i2c_sec_cm	1.340s	119.433us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	2.130s	238.634us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	15.690s	5962.593us	1
target_error_intr				1
	i2c_target_unexp_stop	1.530s	429.372us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	8.090s	2078.785us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				2 test runs
	i2c_host_error_intr	31588199828714818524036340359196211799527323974117061050162783494552114654583	96	UVM_INFO @ 36514596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_stress_all	17275518432235183712465312158433047537374537830181528155665361817394169313567	175	UVM_INFO @ 38114384643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				2 test runs
	i2c_host_stress_all_with_rand_reset	31122006623598416711517476478193386127419432806168733225680454026411930054196	129	UVM_INFO @ 5962593029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	104291272077857631992204312863302105046278553439748887209214020800909977595369	86	UVM_INFO @ 2078785426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	21898284411448746575858277851929191103691646382750243526830389801525971343760	84	UVM_INFO @ 2083435338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'				1 test run
	i2c_target_unexp_stop	27398144065686450398668157985403321394488812580617370736590055680239150914885	79	UVM_ERROR @ 429372142 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A UVM_INFO @ 429372142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!				1 test run
	i2c_target_hrst	98105369236544376823642152134763525788489800813502647640487932540277438650853	79	UVM_INFO @ 11422853390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---