Simulation Results: kmac/unmasked

 
06/05/2026 15:30:23 DVSim: v1.34.0 sha: 238ca4d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.87 %
  • code
  • 88.35 %
  • assert
  • 97.90 %
  • func
  • 92.35 %
  • line
  • 97.36 %
  • branch
  • 94.95 %
  • cond
  • 90.06 %
  • toggle
  • 99.87 %
  • FSM
  • 59.50 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 37.640s 3965.852us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 1.080s 95.341us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 0.890s 38.873us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 5.810s 155.851us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 7.350s 780.524us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 1.470s 226.023us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 0.890s 38.873us 1 1 100.00
kmac_csr_aliasing 7.350s 780.524us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.810s 11.898us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.770s 138.363us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 629.290s 30508.697us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 4.850s 157.135us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 34.210s 10652.438us 1 1 100.00
kmac_test_vectors_sha3_256 28.940s 20659.103us 1 1 100.00
kmac_test_vectors_sha3_384 833.740s 86170.212us 1 1 100.00
kmac_test_vectors_sha3_512 781.620s 117206.399us 1 1 100.00
kmac_test_vectors_shake_128 149.380s 51499.518us 1 1 100.00
kmac_test_vectors_shake_256 72.550s 1619.542us 1 1 100.00
kmac_test_vectors_kmac 2.330s 845.512us 1 1 100.00
kmac_test_vectors_kmac_xof 2.240s 131.651us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 231.590s 15738.536us 1 1 100.00
app 1 1 100.00
kmac_app 174.780s 20423.241us 1 1 100.00
app_with_partial_data 1 1 100.00
kmac_app_with_partial_data 56.750s 5750.384us 1 1 100.00
entropy_refresh 1 1 100.00
kmac_entropy_refresh 26.950s 7513.802us 1 1 100.00
error 1 1 100.00
kmac_error 161.820s 93742.005us 1 1 100.00
key_error 1 1 100.00
kmac_key_error 4.010s 859.383us 1 1 100.00
sideload_invalid 1 1 100.00
kmac_sideload_invalid 1.650s 67.187us 1 1 100.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 12.800s 864.038us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 8.560s 1972.040us 1 1 100.00
entropy_ready_error 1 1 100.00
kmac_entropy_ready_error 32.900s 4214.020us 1 1 100.00
lc_escalation 1 1 100.00
kmac_lc_escalation 14.200s 663.117us 1 1 100.00
stress_all 1 1 100.00
kmac_stress_all 464.600s 12564.736us 1 1 100.00
intr_test 1 1 100.00
kmac_intr_test 0.720s 28.184us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 0.740s 57.769us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 3.710s 1185.146us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 3.710s 1185.146us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 1.080s 95.341us 1 1 100.00
kmac_csr_rw 0.890s 38.873us 1 1 100.00
kmac_csr_aliasing 7.350s 780.524us 1 1 100.00
kmac_same_csr_outstanding 1.860s 135.562us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 1.080s 95.341us 1 1 100.00
kmac_csr_rw 0.890s 38.873us 1 1 100.00
kmac_csr_aliasing 7.350s 780.524us 1 1 100.00
kmac_same_csr_outstanding 1.860s 135.562us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.440s 38.765us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.440s 38.765us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.440s 38.765us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.440s 38.765us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 4.830s 1059.248us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_sec_cm 27.490s 10251.386us 1 1 100.00
kmac_tl_intg_err 2.540s 114.007us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 2.540s 114.007us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 14.200s 663.117us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 37.640s 3965.852us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 231.590s 15738.536us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.440s 38.765us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 27.490s 10251.386us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 27.490s 10251.386us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 27.490s 10251.386us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 37.640s 3965.852us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 14.200s 663.117us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 27.490s 10251.386us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 1 1 100.00
kmac_mubi 141.900s 7283.808us 1 1 100.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 37.640s 3965.852us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
kmac_stress_all_with_rand_reset 26.670s 1691.875us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
kmac_stress_all_with_rand_reset 60542471469508782928591289301859063020255125776292944736051680000231218009227 104
UVM_INFO @ 1691874975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---