Simulation Results: lc_ctrl/volatile_unlock_disabled

 
06/05/2026 15:30:23 DVSim: v1.34.0 sha: 238ca4d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.63 %
  • code
  • 83.29 %
  • assert
  • 94.13 %
  • func
  • 91.46 %
  • line
  • 97.15 %
  • branch
  • 93.56 %
  • cond
  • 79.38 %
  • toggle
  • 85.59 %
  • FSM
  • 60.75 %
Validation stages
V1
100.00%
V2
93.33%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.500s 28.297us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.110s 15.829us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.010s 102.945us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.000s 40.643us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.250s 18.528us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.130s 58.075us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.010s 102.945us 1 1 100.00
lc_ctrl_csr_aliasing 1.250s 18.528us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 6.640s 1295.090us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 8.740s 204.729us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.240s 21.285us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.690s 194.420us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.560s 965.034us 1 1 100.00
lc_errors 0 1 0.00
lc_ctrl_errors 2.080s 54.176us 0 1 0.00
security_escalation 6 7 85.71
lc_ctrl_state_failure 7.560s 965.034us 1 1 100.00
lc_ctrl_prog_failure 2.690s 194.420us 1 1 100.00
lc_ctrl_errors 2.080s 54.176us 0 1 0.00
lc_ctrl_security_escalation 4.680s 680.994us 1 1 100.00
lc_ctrl_jtag_state_failure 35.400s 1675.943us 1 1 100.00
lc_ctrl_jtag_prog_failure 8.570s 392.394us 1 1 100.00
lc_ctrl_jtag_errors 17.050s 3214.927us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 6.000s 283.561us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.400s 1405.849us 1 1 100.00
lc_ctrl_jtag_prog_failure 8.570s 392.394us 1 1 100.00
lc_ctrl_jtag_errors 17.050s 3214.927us 1 1 100.00
lc_ctrl_jtag_access 4.650s 929.140us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 10.100s 2230.815us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.770s 110.213us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.710s 45.069us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 3.520s 680.525us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.540s 361.470us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.320s 78.115us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.100s 1066.820us 1 1 100.00
lc_ctrl_jtag_alert_test 1.460s 36.933us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 10.830s 5531.816us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.890s 38.356us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 19.110s 9625.690us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.190s 134.288us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.460s 134.324us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.460s 134.324us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.110s 15.829us 1 1 100.00
lc_ctrl_csr_rw 1.010s 102.945us 1 1 100.00
lc_ctrl_csr_aliasing 1.250s 18.528us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.340s 16.274us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.110s 15.829us 1 1 100.00
lc_ctrl_csr_rw 1.010s 102.945us 1 1 100.00
lc_ctrl_csr_aliasing 1.250s 18.528us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.340s 16.274us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.360s 634.701us 1 1 100.00
lc_ctrl_tl_intg_err 2.350s 89.500us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.350s 89.500us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 8.740s 204.729us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.560s 965.034us 1 1 100.00
lc_ctrl_sec_cm 5.360s 634.701us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.560s 965.034us 1 1 100.00
lc_ctrl_sec_cm 5.360s 634.701us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.560s 965.034us 1 1 100.00
lc_ctrl_sec_cm 5.360s 634.701us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.560s 965.034us 1 1 100.00
lc_ctrl_sec_cm 5.360s 634.701us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.560s 965.034us 1 1 100.00
lc_ctrl_sec_cm 5.360s 634.701us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.560s 965.034us 1 1 100.00
lc_ctrl_sec_cm 5.360s 634.701us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.560s 965.034us 1 1 100.00
lc_ctrl_sec_cm 5.360s 634.701us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.560s 965.034us 1 1 100.00
lc_ctrl_sec_cm 5.360s 634.701us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.680s 680.994us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 6.640s 1295.090us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.400s 1405.849us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.580s 916.891us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.580s 916.891us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.820s 335.844us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.890s 762.286us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.890s 762.286us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 46.570s 2787.464us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 2 test runs
lc_ctrl_errors 30576818406009802284700766079187364582504646632634524206228307625496102829811 798
UVM_INFO @ 54176132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 108341980424738448921647078736186849235597340673298466406924823464192802720775 4022
UVM_INFO @ 9625689933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 84215292348615112486390448467049957162319708148112755688470903365347015334623 6338
UVM_INFO @ 2787463908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---