Simulation Results: lc_ctrl/volatile_unlock_enabled

 
06/05/2026 15:30:23 DVSim: v1.34.0 sha: 238ca4d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.30 %
  • code
  • 84.04 %
  • assert
  • 93.99 %
  • func
  • 92.88 %
  • line
  • 97.22 %
  • branch
  • 93.66 %
  • cond
  • 79.22 %
  • toggle
  • 85.63 %
  • FSM
  • 64.49 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.400s 355.104us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.800s 175.592us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.050s 16.630us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.150s 37.862us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.120s 24.034us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.360s 309.021us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.050s 16.630us 1 1 100.00
lc_ctrl_csr_aliasing 1.120s 24.034us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.420s 384.111us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 6.170s 210.858us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.740s 14.048us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.210s 307.456us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 8.190s 251.162us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 8.280s 958.772us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 8.190s 251.162us 1 1 100.00
lc_ctrl_prog_failure 2.210s 307.456us 1 1 100.00
lc_ctrl_errors 8.280s 958.772us 1 1 100.00
lc_ctrl_security_escalation 5.260s 1107.625us 1 1 100.00
lc_ctrl_jtag_state_failure 56.460s 12611.051us 1 1 100.00
lc_ctrl_jtag_prog_failure 5.800s 526.817us 1 1 100.00
lc_ctrl_jtag_errors 28.940s 1493.718us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 2.130s 338.618us 1 1 100.00
lc_ctrl_jtag_state_post_trans 7.250s 1201.090us 1 1 100.00
lc_ctrl_jtag_prog_failure 5.800s 526.817us 1 1 100.00
lc_ctrl_jtag_errors 28.940s 1493.718us 1 1 100.00
lc_ctrl_jtag_access 5.900s 2729.452us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 10.960s 943.363us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.230s 495.083us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.110s 280.414us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 14.540s 1595.544us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.440s 224.320us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.700s 137.323us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.780s 355.758us 1 1 100.00
lc_ctrl_jtag_alert_test 1.150s 101.321us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 4.390s 206.723us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.790s 39.334us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 52.770s 5301.263us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.810s 30.548us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.200s 152.694us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.200s 152.694us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.800s 175.592us 1 1 100.00
lc_ctrl_csr_rw 1.050s 16.630us 1 1 100.00
lc_ctrl_csr_aliasing 1.120s 24.034us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.250s 22.539us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.800s 175.592us 1 1 100.00
lc_ctrl_csr_rw 1.050s 16.630us 1 1 100.00
lc_ctrl_csr_aliasing 1.120s 24.034us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.250s 22.539us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 8.620s 362.910us 1 1 100.00
lc_ctrl_tl_intg_err 2.130s 105.364us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.130s 105.364us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 6.170s 210.858us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 8.190s 251.162us 1 1 100.00
lc_ctrl_sec_cm 8.620s 362.910us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 8.190s 251.162us 1 1 100.00
lc_ctrl_sec_cm 8.620s 362.910us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.190s 251.162us 1 1 100.00
lc_ctrl_sec_cm 8.620s 362.910us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.190s 251.162us 1 1 100.00
lc_ctrl_sec_cm 8.620s 362.910us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 8.190s 251.162us 1 1 100.00
lc_ctrl_sec_cm 8.620s 362.910us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.190s 251.162us 1 1 100.00
lc_ctrl_sec_cm 8.620s 362.910us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.190s 251.162us 1 1 100.00
lc_ctrl_sec_cm 8.620s 362.910us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 8.190s 251.162us 1 1 100.00
lc_ctrl_sec_cm 8.620s 362.910us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.260s 1107.625us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.420s 384.111us 1 1 100.00
lc_ctrl_jtag_state_post_trans 7.250s 1201.090us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.000s 388.278us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.000s 388.278us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.990s 395.679us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.670s 607.487us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.670s 607.487us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 26.040s 49120.669us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 105870497895423232653799643009677660770608233527892617447448296933951651307958 5428
UVM_INFO @ 49120668804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---