Simulation Results: otbn

 
06/05/2026 15:30:23 DVSim: v1.34.0 sha: 238ca4d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.00 %
  • code
  • 95.41 %
  • assert
  • 89.57 %
  • func
  • 97.03 %
  • block
  • 99.44 %
  • line
  • 99.57 %
  • branch
  • 92.91 %
  • toggle
  • 91.71 %
  • FSM
  • 97.44 %
Validation stages
V1
100.00%
V2
92.86%
V2S
92.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 11.000s 110.130us 1 1 100.00
single_binary 1 1 100.00
otbn_single 8.000s 116.106us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 30.000s 25.894us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 29.000s 22.688us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 33.000s 70.428us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 30.000s 16.787us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 32.000s 863.316us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 29.000s 22.688us 1 1 100.00
otbn_csr_aliasing 30.000s 16.787us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 53.000s 7210.365us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 25.000s 1029.031us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 35.000s 398.311us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 54.000s 226.781us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 79.000s 847.846us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 30.000s 554.706us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 24.000s 73.556us 1 1 100.00
zero_state_err_urnd 0 1 0.00
otbn_zero_state_err_urnd 5.000s 42.901us 0 1 0.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 9.000s 78.402us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 29.000s 50.617us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 3.000s 20.654us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 4.000s 156.336us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 4.000s 156.336us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 30.000s 25.894us 1 1 100.00
otbn_csr_rw 29.000s 22.688us 1 1 100.00
otbn_csr_aliasing 30.000s 16.787us 1 1 100.00
otbn_same_csr_outstanding 3.000s 14.877us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 30.000s 25.894us 1 1 100.00
otbn_csr_rw 29.000s 22.688us 1 1 100.00
otbn_csr_aliasing 30.000s 16.787us 1 1 100.00
otbn_same_csr_outstanding 3.000s 14.877us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 8.000s 23.175us 1 1 100.00
otbn_dmem_err 30.000s 17.152us 1 1 100.00
internal_integrity 3 4 75.00
otbn_alu_bignum_mod_err 32.000s 93.711us 1 1 100.00
otbn_controller_ispr_rdata_err 188.000s 880.234us 1 1 100.00
otbn_mac_bignum_acc_err 9.000s 217.860us 1 1 100.00
otbn_urnd_err 5.000s 25.205us 0 1 0.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 15.000s 19.837us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 6.000s 39.311us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 4.000s 61.185us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 92.000s 1855.759us 1 1 100.00
otbn_tl_intg_err 9.000s 196.674us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 19.000s 1457.521us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 92.000s 1855.759us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 92.000s 1855.759us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 11.000s 110.130us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 30.000s 17.152us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 8.000s 23.175us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 9.000s 196.674us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 24.000s 73.556us 1 1 100.00
sec_cm_controller_fsm_local_esc 4 5 80.00
otbn_imem_err 8.000s 23.175us 1 1 100.00
otbn_dmem_err 30.000s 17.152us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 42.901us 0 1 0.00
otbn_illegal_mem_acc 15.000s 19.837us 1 1 100.00
otbn_sec_cm 92.000s 1855.759us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 92.000s 1855.759us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 8.000s 116.106us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 8.000s 23.175us 1 1 100.00
otbn_dmem_err 30.000s 17.152us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 42.901us 0 1 0.00
otbn_illegal_mem_acc 15.000s 19.837us 1 1 100.00
otbn_sec_cm 92.000s 1855.759us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 92.000s 1855.759us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 24.000s 73.556us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 8.000s 23.175us 1 1 100.00
otbn_dmem_err 30.000s 17.152us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 42.901us 0 1 0.00
otbn_illegal_mem_acc 15.000s 19.837us 1 1 100.00
otbn_sec_cm 92.000s 1855.759us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 92.000s 1855.759us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 8.000s 116.106us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 30.000s 17.238us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 6.000s 21.344us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 15.000s 161.648us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 15.000s 161.648us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 10.000s 23.111us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 92.000s 1855.759us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 92.000s 1855.759us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 15.000s 46.480us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 92.000s 1855.759us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 92.000s 1855.759us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 17.000s 399.747us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 17.000s 399.747us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 4.000s 9.991us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 8.000s 116.106us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 8.000s 116.106us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 8.000s 116.106us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 79.000s 847.846us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 8.000s 116.106us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 8.000s 116.106us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 29.000s 122.166us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 8.000s 116.106us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 92.000s 1855.759us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 195.000s 2059.345us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 7.000s 32.921us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1237) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
otbn_stress_all_with_rand_reset 113323496526582941506654451347243227119696041935719798996077887117090139004080 284
UVM_INFO @ 2059345010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.u_otbn_core.u_otbn_rnd.u_xoshiro256pp.xoshiro_q cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) 1 test run
otbn_zero_state_err_urnd 66839803958906435278144708791407665759874399307403378934287491477878033837626 105
UVM_INFO @ 42901204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.edn_urnd_ack cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) 1 test run
otbn_urnd_err 78392918883586196849223942874543399774030785961880332678388233907149197633116 108
UVM_INFO @ 25204613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---