Simulation Results: otp_ctrl

 
06/05/2026 15:30:23 DVSim: v1.34.0 sha: 238ca4d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.47 %
  • code
  • 79.15 %
  • assert
  • 93.67 %
  • func
  • 74.58 %
  • line
  • 88.70 %
  • branch
  • 84.30 %
  • cond
  • 92.51 %
  • toggle
  • 85.60 %
  • FSM
  • 44.62 %
Validation stages
V1
100.00%
V2
90.00%
V2S
88.89%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 2.200s 126.191us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 7.010s 1773.539us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.480s 76.901us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.660s 98.177us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 4.330s 218.325us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 3.770s 81.864us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.580s 75.666us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.660s 98.177us 1 1 100.00
otp_ctrl_csr_aliasing 3.770s 81.864us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.560s 559.446us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.420s 535.207us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 15.590s 2827.992us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 2.730s 162.211us 1 1 100.00
partition_check 0 2 0.00
otp_ctrl_background_chks 22.020s 3997.202us 0 1 0.00
otp_ctrl_check_fail 4.870s 559.486us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 7.180s 923.069us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 17.050s 6756.856us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 7.890s 644.798us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 8.600s 673.665us 1 1 100.00
otp_ctrl_parallel_lc_esc 9.190s 784.995us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 19.060s 879.548us 1 1 100.00
otp_macro_errors 1 1 100.00
otp_ctrl_macro_errs 16.950s 2554.646us 1 1 100.00
test_access 1 1 100.00
otp_ctrl_test_access 20.010s 1370.742us 1 1 100.00
stress_all 1 1 100.00
otp_ctrl_stress_all 74.470s 9585.211us 1 1 100.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.280s 76.771us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.740s 182.405us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 2.790s 101.409us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 2.790s 101.409us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.480s 76.901us 1 1 100.00
otp_ctrl_csr_rw 1.660s 98.177us 1 1 100.00
otp_ctrl_csr_aliasing 3.770s 81.864us 1 1 100.00
otp_ctrl_same_csr_outstanding 1.840s 177.602us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.480s 76.901us 1 1 100.00
otp_ctrl_csr_rw 1.660s 98.177us 1 1 100.00
otp_ctrl_csr_aliasing 3.770s 81.864us 1 1 100.00
otp_ctrl_same_csr_outstanding 1.840s 177.602us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 115.840s 26235.159us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 115.840s 26235.159us 1 1 100.00
otp_ctrl_tl_intg_err 13.650s 2489.524us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 115.840s 26235.159us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 115.840s 26235.159us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 13.650s 2489.524us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 7.010s 1773.539us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 7.010s 1773.539us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 115.840s 26235.159us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 115.840s 26235.159us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 115.840s 26235.159us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 115.840s 26235.159us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 115.840s 26235.159us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 115.840s 26235.159us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 115.840s 26235.159us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 115.840s 26235.159us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 115.840s 26235.159us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 115.840s 26235.159us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 115.840s 26235.159us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 115.840s 26235.159us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 115.840s 26235.159us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 115.840s 26235.159us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 115.840s 26235.159us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 9.190s 784.995us 1 1 100.00
otp_ctrl_sec_cm 115.840s 26235.159us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 9.190s 784.995us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 9.190s 784.995us 1 1 100.00
sec_cm_part_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 9.190s 784.995us 1 1 100.00
otp_ctrl_macro_errs 16.950s 2554.646us 1 1 100.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 9.190s 784.995us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 9.190s 784.995us 1 1 100.00
otp_ctrl_sec_cm 115.840s 26235.159us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 9.190s 784.995us 1 1 100.00
otp_ctrl_sec_cm 115.840s 26235.159us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 9.190s 784.995us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 9.190s 784.995us 1 1 100.00
sec_cm_part_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 9.190s 784.995us 1 1 100.00
otp_ctrl_macro_errs 16.950s 2554.646us 1 1 100.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 9.190s 784.995us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 9.190s 784.995us 1 1 100.00
otp_ctrl_sec_cm 115.840s 26235.159us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 2.730s 162.211us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 4.870s 559.486us 0 1 0.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 17.050s 6756.856us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 17.050s 6756.856us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 17.050s 6756.856us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 17.050s 6756.856us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 17.050s 6756.856us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 7.010s 1773.539us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 17.050s 6756.856us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 7.010s 1773.539us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 115.840s 26235.159us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 7.180s 923.069us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 7.010s 1773.539us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 7.010s 1773.539us 1 1 100.00
sec_cm_macro_mem_integrity 1 1 100.00
otp_ctrl_macro_errs 16.950s 2554.646us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 11.920s 5877.052us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
otp_ctrl_stress_all_with_rand_reset 99.950s 7237.433us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1315) [otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_check_error does not trigger! 1 test run
otp_ctrl_background_chks 21016681705144900284166290542903736187058404108013448126942230668856182707006 28373
UVM_INFO @ 3997202387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 1 test run
otp_ctrl_check_fail 64041953961820289197213043156033329354990163650476689748956590880279823550859 2829
UVM_INFO @ 559485838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---