Simulation Results: pattgen

 
06/05/2026 15:30:23 DVSim: v1.34.0 sha: 238ca4d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.08 %
  • code
  • 98.87 %
  • assert
  • 96.95 %
  • func
  • 89.42 %
  • block
  • 100.00 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • toggle
  • 96.61 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
0.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pattgen_smoke 3.000s 418.220us 1 1 100.00
csr_hw_reset 1 1 100.00
pattgen_csr_hw_reset 1.000s 17.979us 1 1 100.00
csr_rw 1 1 100.00
pattgen_csr_rw 2.000s 42.605us 1 1 100.00
csr_bit_bash 1 1 100.00
pattgen_csr_bit_bash 2.000s 1100.864us 1 1 100.00
csr_aliasing 1 1 100.00
pattgen_csr_aliasing 2.000s 29.248us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pattgen_csr_mem_rw_with_rand_reset 1.000s 29.290us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pattgen_csr_rw 2.000s 42.605us 1 1 100.00
pattgen_csr_aliasing 2.000s 29.248us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
perf 1 1 100.00
pattgen_perf 32.000s 1346.129us 1 1 100.00
cnt_rollover 1 1 100.00
cnt_rollover 11.000s 5501.337us 1 1 100.00
error 1 1 100.00
pattgen_error 1.000s 37.596us 1 1 100.00
stress_all 0 1 0.00
pattgen_stress_all 2.000s 505.645us 0 1 0.00
alert_test 1 1 100.00
pattgen_alert_test 2.000s 18.228us 1 1 100.00
intr_test 1 1 100.00
pattgen_intr_test 1.000s 42.156us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pattgen_tl_errors 2.000s 75.498us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pattgen_tl_errors 2.000s 75.498us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 17.979us 1 1 100.00
pattgen_csr_rw 2.000s 42.605us 1 1 100.00
pattgen_csr_aliasing 2.000s 29.248us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 45.322us 1 1 100.00
tl_d_partial_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 17.979us 1 1 100.00
pattgen_csr_rw 2.000s 42.605us 1 1 100.00
pattgen_csr_aliasing 2.000s 29.248us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 45.322us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pattgen_tl_intg_err 1.000s 156.749us 1 1 100.00
pattgen_sec_cm 1.000s 193.164us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pattgen_tl_intg_err 1.000s 156.749us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
pattgen_stress_all_with_rand_reset 54.000s 5718.259us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
pattgen_inactive_level 18.000s 10062.603us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) 1 test run
pattgen_inactive_level 62106449161077587465899735346932138138533249572238618186572458623838255275484 99
UVM_INFO @ 10062603360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1237) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
pattgen_stress_all_with_rand_reset 45068301680688401230705733421481409308527196769900912916594813976092790013979 170
UVM_ERROR @ 2763743487 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2763743487 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/5
UVM_INFO @ 2763903487 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: 1 test run
pattgen_stress_all 70204596149340847721474694123535195964015090723925808663067883433752552788384 132
------------------------------------
Name Type Size Value
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exp_item pattgen_item - @10275