Simulation Results: pwrmgr

 
06/05/2026 15:30:23 DVSim: v1.34.0 sha: 238ca4d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.69 %
  • code
  • 94.60 %
  • assert
  • 96.08 %
  • func
  • 96.38 %
  • line
  • 98.92 %
  • branch
  • 95.42 %
  • cond
  • 94.63 %
  • toggle
  • 90.02 %
  • FSM
  • 94.00 %
Validation stages
V1
100.00%
V2
93.33%
V2S
80.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.770s 25.668us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.650s 24.341us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.730s 30.149us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 2.540s 386.791us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 1.090s 164.978us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.890s 252.682us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.730s 30.149us 1 1 100.00
pwrmgr_csr_aliasing 1.090s 164.978us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.690s 129.948us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.690s 129.948us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.870s 31.291us 1 1 100.00
pwrmgr_lowpower_invalid 0.630s 82.954us 1 1 100.00
reset 1 2 50.00
pwrmgr_reset 0.890s 1000.000us 0 1 0.00
pwrmgr_reset_invalid 0.770s 232.913us 1 1 100.00
main_power_glitch_reset 0 1 0.00
pwrmgr_reset 0.890s 1000.000us 0 1 0.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.610s 26.079us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.920s 76.636us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 1.020s 146.550us 1 1 100.00
stress_all 1 1 100.00
pwrmgr_stress_all 1.950s 907.548us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.660s 24.529us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.550s 251.867us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.550s 251.867us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.650s 24.341us 1 1 100.00
pwrmgr_csr_rw 0.730s 30.149us 1 1 100.00
pwrmgr_csr_aliasing 1.090s 164.978us 1 1 100.00
pwrmgr_same_csr_outstanding 0.780s 58.876us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.650s 24.341us 1 1 100.00
pwrmgr_csr_rw 0.730s 30.149us 1 1 100.00
pwrmgr_csr_aliasing 1.090s 164.978us 1 1 100.00
pwrmgr_same_csr_outstanding 0.780s 58.876us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
pwrmgr_tl_intg_err 0.610s 10.671us 0 1 0.00
pwrmgr_sec_cm 0.690s 22.601us 0 1 0.00
prim_count_check 0 1 0.00
pwrmgr_sec_cm 0.690s 22.601us 0 1 0.00
prim_fsm_check 0 1 0.00
pwrmgr_sec_cm 0.690s 22.601us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
pwrmgr_tl_intg_err 0.610s 10.671us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.990s 901.332us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 1 1 100.00
pwrmgr_wakeup_reset 0.610s 26.079us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.770s 110.110us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.780s 31.589us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 0 1 0.00
pwrmgr_sec_cm 0.690s 22.601us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
pwrmgr_sec_cm 0.690s 22.601us 0 1 0.00
sec_cm_fsm_terminal 0 1 0.00
pwrmgr_sec_cm 0.690s 22.601us 0 1 0.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.680s 34.478us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.700s 48.476us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.670s 36.285us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.730s 30.149us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.730s 30.149us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 0 1 0.00
pwrmgr_escalation_timeout 0.720s 331.382us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 6.440s 9890.432us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [pwrmgr_common_vseq] expect alert:fatal_fault to fire 2 test runs
pwrmgr_tl_intg_err 15637655897485379449830316630280472364696002875520705645704130546018021964757 78
UVM_INFO @ 10670968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_sec_cm 90944874129136480446945154514104050551496664402458807771893063410201388782824 84
UVM_INFO @ 22601248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
pwrmgr_reset 10573766915733263710886478674887586263557634575288314401237488682134348489882 115
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((!clk_en) || status)' 1 test run
pwrmgr_escalation_timeout 39809839276424954624103066762655627688481548276383826331907734364333098974354 79
UVM_ERROR @ 331382232 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 331382232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---