Simulation Results: rom_ctrl/32kb

 
06/05/2026 15:30:23 DVSim: v1.34.0 sha: 238ca4d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.96 %
  • code
  • 97.43 %
  • assert
  • 96.80 %
  • func
  • 96.66 %
  • line
  • 99.32 %
  • branch
  • 98.18 %
  • cond
  • 96.58 %
  • toggle
  • 99.75 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 4.100s 236.793us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 4.640s 130.884us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 4.010s 209.694us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.770s 538.855us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.730s 136.086us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 3.790s 136.687us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 4.010s 209.694us 1 1 100.00
rom_ctrl_csr_aliasing 3.730s 136.086us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 4.570s 1042.877us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.050s 371.022us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 3.930s 386.872us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 12.680s 1416.346us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 7.170s 537.303us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 2.900s 794.096us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 5.540s 166.165us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 5.540s 166.165us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.640s 130.884us 1 1 100.00
rom_ctrl_csr_rw 4.010s 209.694us 1 1 100.00
rom_ctrl_csr_aliasing 3.730s 136.086us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.460s 173.659us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.640s 130.884us 1 1 100.00
rom_ctrl_csr_rw 4.010s 209.694us 1 1 100.00
rom_ctrl_csr_aliasing 3.730s 136.086us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.460s 173.659us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 47.460s 1262.210us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 19.300s 3038.309us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 194.930s 2762.290us 1 1 100.00
rom_ctrl_tl_intg_err 24.690s 244.165us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 194.930s 2762.290us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 194.930s 2762.290us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 47.460s 1262.210us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 47.460s 1262.210us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 47.460s 1262.210us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 47.460s 1262.210us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 47.460s 1262.210us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 194.930s 2762.290us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 194.930s 2762.290us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 4.100s 236.793us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 4.100s 236.793us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 4.100s 236.793us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 24.690s 244.165us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 47.460s 1262.210us 1 1 100.00
rom_ctrl_kmac_err_chk 7.170s 537.303us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 47.460s 1262.210us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 47.460s 1262.210us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 47.460s 1262.210us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 19.300s 3038.309us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 194.930s 2762.290us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 67.270s 4996.865us 1 1 100.00