Simulation Results: rstmgr

 
06/05/2026 15:30:23 DVSim: v1.34.0 sha: 238ca4d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.09 %
  • code
  • 99.30 %
  • assert
  • 97.72 %
  • func
  • 97.26 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.68 %
  • toggle
  • 99.16 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.400s 125.778us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.850s 126.666us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.870s 82.538us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 4.580s 491.161us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 2.000s 344.073us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.080s 134.483us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.870s 82.538us 1 1 100.00
rstmgr_csr_aliasing 2.000s 344.073us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.870s 142.917us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.610s 310.040us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.040s 145.617us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 4.100s 975.620us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 4.100s 975.620us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 4.100s 975.620us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 4.100s 975.620us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 26.060s 9601.825us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.850s 70.564us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.280s 112.399us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.280s 112.399us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.850s 126.666us 1 1 100.00
rstmgr_csr_rw 0.870s 82.538us 1 1 100.00
rstmgr_csr_aliasing 2.000s 344.073us 1 1 100.00
rstmgr_same_csr_outstanding 1.840s 243.280us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.850s 126.666us 1 1 100.00
rstmgr_csr_rw 0.870s 82.538us 1 1 100.00
rstmgr_csr_aliasing 2.000s 344.073us 1 1 100.00
rstmgr_same_csr_outstanding 1.840s 243.280us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 22.630s 17854.464us 1 1 100.00
rstmgr_tl_intg_err 1.740s 505.662us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 22.630s 17854.464us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 22.630s 17854.464us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 1.740s 505.662us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.010s 107.826us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 4.070s 1279.699us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.070s 301.914us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 22.630s 17854.464us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.870s 82.538us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.870s 82.538us 1 1 100.00