Simulation Results: rv_timer

 
06/05/2026 15:30:23 DVSim: v1.34.0 sha: 238ca4d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.90 %
  • code
  • 100.00 %
  • assert
  • 96.82 %
  • func
  • 90.88 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.890s 205.508us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.670s 17.826us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.580s 15.316us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.630s 567.680us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.960s 278.085us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 1.210s 661.883us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.580s 15.316us 1 1 100.00
rv_timer_csr_aliasing 0.960s 278.085us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 1.500s 414.572us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 1.640s 4054.983us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 565.460s 1808615.555us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 565.460s 1808615.555us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 0.600s 99.800us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.570s 37.928us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.550s 20.693us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.770s 171.796us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.770s 171.796us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.670s 17.826us 1 1 100.00
rv_timer_csr_rw 0.580s 15.316us 1 1 100.00
rv_timer_csr_aliasing 0.960s 278.085us 1 1 100.00
rv_timer_same_csr_outstanding 0.730s 39.332us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.670s 17.826us 1 1 100.00
rv_timer_csr_rw 0.580s 15.316us 1 1 100.00
rv_timer_csr_aliasing 0.960s 278.085us 1 1 100.00
rv_timer_same_csr_outstanding 0.730s 39.332us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.730s 148.192us 1 1 100.00
rv_timer_tl_intg_err 1.230s 2033.647us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.230s 2033.647us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.620s 226.867us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.650s 84.296us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 20.280s 14696.508us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 2 test runs
rv_timer_min 101927750471250852151566631942715274491917536539296759025471980486290037237574 77
UVM_INFO @ 226866818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 52732783580959976374569158106222516787549751625965426530295267441441498735085 75
UVM_INFO @ 414572345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 19235453673122311122053430647735684214158761278448013492524332504508449608620 75
UVM_INFO @ 84296091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---