Simulation Results: spi_device/2p

 
06/05/2026 15:30:23 DVSim: v1.34.0 sha: 238ca4d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.31 %
  • code
  • 94.16 %
  • assert
  • 94.62 %
  • func
  • 76.14 %
  • line
  • 99.13 %
  • branch
  • 98.42 %
  • cond
  • 96.13 %
  • toggle
  • 87.74 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 32.730s 37038.744us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 0.930s 16.782us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 2.050s 68.349us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 18.380s 1275.285us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 6.730s 6005.482us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 1.630s 48.548us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 2.050s 68.349us 1 1 100.00
spi_device_csr_aliasing 6.730s 6005.482us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.730s 45.671us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 2.060s 59.676us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.800s 62.675us 1 1 100.00
mem_parity 1 1 100.00
spi_device_mem_parity 1.350s 138.286us 1 1 100.00
mem_cfg 1 1 100.00
spi_device_ram_cfg 0.860s 16.698us 1 1 100.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.710s 551.768us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.710s 551.768us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 8.450s 38264.792us 1 1 100.00
spi_device_tpm_sts_read 0.960s 509.007us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 0.680s 11.516us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 7.530s 5665.587us 1 1 100.00
spi_device_flash_all 99.960s 33385.891us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 7.390s 10245.300us 1 1 100.00
spi_device_flash_all 99.960s 33385.891us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 7.390s 10245.300us 1 1 100.00
spi_device_flash_all 99.960s 33385.891us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 99.960s 33385.891us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 5.620s 1522.209us 1 1 100.00
spi_device_flash_all 99.960s 33385.891us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 5.620s 1522.209us 1 1 100.00
spi_device_flash_all 99.960s 33385.891us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 5.620s 1522.209us 1 1 100.00
spi_device_flash_all 99.960s 33385.891us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 5.620s 1522.209us 1 1 100.00
spi_device_flash_all 99.960s 33385.891us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 5.620s 1522.209us 1 1 100.00
spi_device_flash_all 99.960s 33385.891us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 2.170s 147.082us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 11.580s 6621.664us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 11.580s 6621.664us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 11.580s 6621.664us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 27.310s 10924.900us 1 1 100.00
spi_device_read_buffer_direct 2.780s 260.228us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 11.580s 6621.664us 1 1 100.00
spi_device_flash_all 99.960s 33385.891us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 99.960s 33385.891us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 99.960s 33385.891us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 16.570s 13999.305us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 16.570s 13999.305us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 32.730s 37038.744us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 34.180s 10244.318us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 297.660s 51971.374us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.720s 47.328us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.730s 16.641us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 1.980s 142.345us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 1.980s 142.345us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 0.930s 16.782us 1 1 100.00
spi_device_csr_rw 2.050s 68.349us 1 1 100.00
spi_device_csr_aliasing 6.730s 6005.482us 1 1 100.00
spi_device_same_csr_outstanding 2.320s 75.311us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 0.930s 16.782us 1 1 100.00
spi_device_csr_rw 2.050s 68.349us 1 1 100.00
spi_device_csr_aliasing 6.730s 6005.482us 1 1 100.00
spi_device_same_csr_outstanding 2.320s 75.311us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.100s 103.531us 1 1 100.00
spi_device_tl_intg_err 6.360s 360.965us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 6.360s 360.965us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 66.480s 63436.529us 1 1 100.00