Simulation Results: spi_host

 
06/05/2026 15:30:23 DVSim: v1.34.0 sha: 238ca4d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.73 %
  • code
  • 94.98 %
  • assert
  • 94.13 %
  • func
  • 89.08 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 87.81 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 11.000s 1726.236us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 2.000s 29.117us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 34.226us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 3.000s 1700.164us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 24.139us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 66.159us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 34.226us 1 1 100.00
spi_host_csr_aliasing 1.000s 24.139us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 17.167us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 55.578us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 2.000s 22.486us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 2.000s 273.985us 1 1 100.00
spi_host_error_cmd 1.000s 53.626us 1 1 100.00
spi_host_event 23.000s 816.214us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 2.000s 124.082us 1 1 100.00
speed 1 1 100.00
spi_host_speed 2.000s 124.082us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 2.000s 124.082us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 2.000s 74.343us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 34.703us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 2.000s 124.082us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 2.000s 124.082us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 11.000s 1726.236us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 11.000s 1726.236us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 3.000s 170.789us 1 1 100.00
spien 1 1 100.00
spi_host_spien 2.000s 574.724us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 25.000s 5279.765us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 2.000s 25.514us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 2.000s 273.985us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 1.000s 17.597us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 21.683us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 2.000s 148.262us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 2.000s 148.262us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 2.000s 29.117us 1 1 100.00
spi_host_csr_rw 1.000s 34.226us 1 1 100.00
spi_host_csr_aliasing 1.000s 24.139us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 28.818us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 2.000s 29.117us 1 1 100.00
spi_host_csr_rw 1.000s 34.226us 1 1 100.00
spi_host_csr_aliasing 1.000s 24.139us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 28.818us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 2.000s 102.665us 1 1 100.00
spi_host_sec_cm 1.000s 247.826us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 102.665us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_host_upper_range_clkdiv 78.000s 4744.041us 1 1 100.00