Simulation Results: sram_ctrl/main

 
06/05/2026 15:30:23 DVSim: v1.34.0 sha: 238ca4d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.69 %
  • code
  • 96.80 %
  • assert
  • 96.46 %
  • func
  • 90.80 %
  • block
  • 96.08 %
  • line
  • 96.81 %
  • branch
  • 94.33 %
  • toggle
  • 96.04 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 7.000s 1462.464us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 47.697us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 58.285us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.000s 29.472us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 37.107us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 365.565us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 58.285us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 37.107us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 90.000s 2805.578us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 53.000s 6263.023us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 21.000s 17381.282us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 110.000s 34633.194us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 145.000s 29374.395us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 27.000s 11964.845us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 40.000s 11517.667us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 21.000s 54222.986us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 4.000s 1406.174us 1 1 100.00
sram_ctrl_partial_access_b2b 132.000s 16501.753us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 5.000s 2780.312us 1 1 100.00
sram_ctrl_throughput_w_partial_write 4.000s 675.225us 1 1 100.00
sram_ctrl_throughput_w_readback 5.000s 2168.813us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 11.000s 2841.581us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 3.000s 344.896us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 300.000s 473522.028us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 74.507us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 126.485us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 126.485us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 47.697us 1 1 100.00
sram_ctrl_csr_rw 1.000s 58.285us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 37.107us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 47.890us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 47.697us 1 1 100.00
sram_ctrl_csr_rw 1.000s 58.285us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 37.107us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 47.890us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 14.000s 40935.224us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 733.322us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 834.263us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 733.322us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 834.263us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 11.000s 2841.581us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 11.000s 2841.581us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 58.285us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 21.000s 54222.986us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 21.000s 54222.986us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 21.000s 54222.986us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 40.000s 11517.667us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 4.000s 797.316us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 14.000s 40935.224us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 3.000s 2778.057us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 7.000s 1462.464us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 7.000s 1462.464us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 21.000s 54222.986us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 733.322us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 40.000s 11517.667us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 733.322us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 733.322us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 7.000s 1462.464us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 733.322us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 11.000s 2706.539us 1 1 100.00