Simulation Results: sram_ctrl/ret

 
06/05/2026 15:30:23 DVSim: v1.34.0 sha: 238ca4d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.14 %
  • code
  • 82.78 %
  • assert
  • 96.43 %
  • func
  • 94.20 %
  • block
  • 93.05 %
  • line
  • 94.06 %
  • branch
  • 88.11 %
  • toggle
  • 82.28 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 64.000us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 54.680us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 23.555us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 337.365us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 25.058us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 1.000s 138.141us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 23.555us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 25.058us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 7.000s 272.448us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 3.000s 113.852us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 5.000s 303.105us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 117.000s 4621.732us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 5.000s 1571.711us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 8.000s 522.499us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 3.000s 215.555us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 6.000s 1307.288us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 1.000s 35.540us 1 1 100.00
sram_ctrl_partial_access_b2b 140.000s 22085.433us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 1.000s 41.313us 1 1 100.00
sram_ctrl_throughput_w_partial_write 1.000s 123.761us 1 1 100.00
sram_ctrl_throughput_w_readback 2.000s 47.165us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 6.000s 962.290us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.000s 218.633us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 13.000s 1267.356us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 14.560us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 29.082us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 29.082us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 54.680us 1 1 100.00
sram_ctrl_csr_rw 1.000s 23.555us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 25.058us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 86.195us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 54.680us 1 1 100.00
sram_ctrl_csr_rw 1.000s 23.555us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 25.058us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 86.195us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 906.773us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 931.368us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 368.966us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 931.368us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 368.966us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 6.000s 962.290us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 6.000s 962.290us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 23.555us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 6.000s 1307.288us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 6.000s 1307.288us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 6.000s 1307.288us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 3.000s 215.555us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 2.000s 37.571us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 906.773us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 2.000s 42.284us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 64.000us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 64.000us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 6.000s 1307.288us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 931.368us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 3.000s 215.555us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 931.368us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 931.368us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 64.000us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 931.368us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 22.000s 15847.697us 1 1 100.00