Simulation Results: sysrst_ctrl

 
06/05/2026 15:30:23 DVSim: v1.34.0 sha: 238ca4d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.37 %
  • code
  • 91.11 %
  • assert
  • 90.61 %
  • func
  • 65.38 %
  • line
  • 96.26 %
  • branch
  • 96.55 %
  • cond
  • 93.52 %
  • toggle
  • 100.00 %
  • FSM
  • 69.23 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 2.780s 2113.992us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 4.150s 2449.560us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 1.170s 2235.036us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 1.630s 2307.540us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 2.920s 4075.167us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 1.780s 2050.533us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 60.140s 40531.211us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 2.470s 2712.845us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 1.270s 2130.671us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 1.780s 2050.533us 1 1 100.00
sysrst_ctrl_csr_aliasing 2.470s 2712.845us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 97.810s 67288.054us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 105.080s 50226.583us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 7.800s 3451.684us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 2.700s 2946.041us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 1.600s 2545.911us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 4.480s 2084.257us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 193.580s 435691.137us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 1.850s 2634.215us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 131.120s 658516.781us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 19.400s 30897.024us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 10.780s 6282.166us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 1.660s 2022.606us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 4.690s 2018.325us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 4.410s 2192.631us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 4.410s 2192.631us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 2.920s 4075.167us 1 1 100.00
sysrst_ctrl_csr_rw 1.780s 2050.533us 1 1 100.00
sysrst_ctrl_csr_aliasing 2.470s 2712.845us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 9.650s 4655.009us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 2.920s 4075.167us 1 1 100.00
sysrst_ctrl_csr_rw 1.780s 2050.533us 1 1 100.00
sysrst_ctrl_csr_aliasing 2.470s 2712.845us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 9.650s 4655.009us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 24.100s 22022.040us 1 1 100.00
sysrst_ctrl_tl_intg_err 24.150s 42857.665us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 24.150s 42857.665us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 8.760s 4142.955us 1 1 100.00