Simulation Results: uart

 
06/05/2026 15:30:23 DVSim: v1.34.0 sha: 238ca4d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.85 %
  • code
  • 94.63 %
  • assert
  • 97.12 %
  • func
  • 56.81 %
  • line
  • 98.86 %
  • branch
  • 96.27 %
  • cond
  • 91.83 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 7.270s 5975.770us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.660s 39.504us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.660s 13.163us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.660s 509.541us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.810s 125.872us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.740s 24.905us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.660s 13.163us 1 1 100.00
uart_csr_aliasing 0.810s 125.872us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 42.020s 79561.833us 1 1 100.00
parity 2 2 100.00
uart_smoke 7.270s 5975.770us 1 1 100.00
uart_tx_rx 42.020s 79561.833us 1 1 100.00
parity_error 2 2 100.00
uart_intr 22.420s 18527.143us 1 1 100.00
uart_rx_parity_err 35.080s 125066.487us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 42.020s 79561.833us 1 1 100.00
uart_intr 22.420s 18527.143us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 22.430s 85265.457us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 129.800s 91394.781us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 88.110s 94499.321us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 22.420s 18527.143us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 22.420s 18527.143us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 22.420s 18527.143us 1 1 100.00
perf 1 1 100.00
uart_perf 70.930s 7612.410us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 2.090s 1729.409us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 2.090s 1729.409us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 0.900s 473.113us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 1.100s 4826.229us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 2.760s 1609.514us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 6.610s 3275.996us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 423.520s 115964.923us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 92.860s 331834.309us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.610s 40.739us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.690s 15.841us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.320s 96.001us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.320s 96.001us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.660s 39.504us 1 1 100.00
uart_csr_rw 0.660s 13.163us 1 1 100.00
uart_csr_aliasing 0.810s 125.872us 1 1 100.00
uart_same_csr_outstanding 0.800s 58.845us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.660s 39.504us 1 1 100.00
uart_csr_rw 0.660s 13.163us 1 1 100.00
uart_csr_aliasing 0.810s 125.872us 1 1 100.00
uart_same_csr_outstanding 0.800s 58.845us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.740s 39.383us 1 1 100.00
uart_tl_intg_err 1.150s 151.070us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.150s 151.070us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 22.860s 2951.258us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * 1 test run
uart_noise_filter 71505118728650366806671549936095222225656226652584136564647249092277423651236 74
UVM_ERROR @ 284495107 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 284495107 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 378534697 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 3, clk_pulses: 0
UVM_ERROR @ 378611621 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (169 [0xa9] vs 251 [0xfb]) reg name: uart_reg_block.rdata