Simulation Results: adc_ctrl

 
07/05/2026 15:30:24 DVSim: v1.34.0 sha: 9bbcf3f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 65.18 %
  • code
  • 91.74 %
  • assert
  • 90.92 %
  • func
  • 12.89 %
  • line
  • 98.03 %
  • branch
  • 96.29 %
  • cond
  • 86.23 %
  • toggle
  • 99.76 %
  • FSM
  • 78.38 %
Validation stages
V1
100.00%
V2
52.63%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 10.980s 5707.275us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 1.680s 917.860us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 1.700s 552.237us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 13.240s 26371.588us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 2.710s 544.850us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.700s 437.415us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 1.700s 552.237us 1 1 100.00
adc_ctrl_csr_aliasing 2.710s 544.850us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 0 1 0.00
adc_ctrl_filters_polled 1.220s 367.113us 0 1 0.00
filters_polled_fixed 0 1 0.00
adc_ctrl_filters_polled_fixed 1.000s 450.184us 0 1 0.00
filters_interrupt 0 1 0.00
adc_ctrl_filters_interrupt 0.910s 380.184us 0 1 0.00
filters_interrupt_fixed 0 1 0.00
adc_ctrl_filters_interrupt_fixed 0.790s 360.631us 0 1 0.00
filters_wakeup 0 1 0.00
adc_ctrl_filters_wakeup 0.730s 493.135us 0 1 0.00
filters_wakeup_fixed 0 1 0.00
adc_ctrl_filters_wakeup_fixed 0.840s 345.939us 0 1 0.00
filters_both 0 1 0.00
adc_ctrl_filters_both 2.000s 457.548us 0 1 0.00
clock_gating 0 1 0.00
adc_ctrl_clock_gating 0.770s 303.620us 0 1 0.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 1.860s 2997.918us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 59.770s 36617.824us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 135.700s 74642.786us 1 1 100.00
stress_all 0 1 0.00
adc_ctrl_stress_all 11.090s 6878.446us 0 1 0.00
alert_test 1 1 100.00
adc_ctrl_alert_test 1.570s 494.954us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 1.260s 431.078us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 2.810s 608.424us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 2.810s 608.424us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.680s 917.860us 1 1 100.00
adc_ctrl_csr_rw 1.700s 552.237us 1 1 100.00
adc_ctrl_csr_aliasing 2.710s 544.850us 1 1 100.00
adc_ctrl_same_csr_outstanding 5.000s 2735.613us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.680s 917.860us 1 1 100.00
adc_ctrl_csr_rw 1.700s 552.237us 1 1 100.00
adc_ctrl_csr_aliasing 2.710s 544.850us 1 1 100.00
adc_ctrl_same_csr_outstanding 5.000s 2735.613us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 3.900s 7683.309us 1 1 100.00
adc_ctrl_tl_intg_err 10.020s 8484.047us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 10.020s 8484.047us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
adc_ctrl_stress_all_with_rand_reset 2.350s 973.020us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [*, *] 10 test runs
adc_ctrl_filters_polled 75743672891119146083592715986756835895338338680434355905635786922320549838969 389
UVM_INFO @ 367113221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 803076028917699787894906728071501801242028950470910404495734539096003197815 389
UVM_INFO @ 450184307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 33942503044471427901645050126869271894274659300143822633299429583306475670396 389
UVM_INFO @ 380183816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 38262834256254687122511203595887388933014141971854498556200923359472686623721 389
UVM_INFO @ 360631118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 37729170248454982230672831049284824660533814524640525989115901525690559939442 389
UVM_INFO @ 493135363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 57281316759795566697843524706440143086835508678151970663151903557775396699417 389
UVM_INFO @ 345938753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 29679181789646973605467266141318267799608203239990090728317201157263019821814 389
UVM_INFO @ 303620044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 83027414587600991725575683248252131674292673082884271848820489076437929203221 389
UVM_INFO @ 457547800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 103050490791362367273255497345752968946198805214049264097786248825270536254145 395
UVM_INFO @ 973020459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 36398189724845233285202056837299972731280126267653898081087884759928615996066 405
UVM_INFO @ 6878446135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---