Simulation Results: aes/masked

 
07/05/2026 15:30:24 DVSim: v1.34.0 sha: 9bbcf3f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.44 %
  • code
  • 93.59 %
  • assert
  • 98.23 %
  • func
  • 73.50 %
  • block
  • 94.31 %
  • line
  • 96.00 %
  • branch
  • 87.24 %
  • toggle
  • 97.81 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
88.24%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 60.124us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 77.002us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 52.247us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 56.551us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 5.000s 1588.433us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 134.364us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 97.270us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 56.551us 1 1 100.00
aes_csr_aliasing 3.000s 134.364us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 77.002us 1 1 100.00
aes_config_error 4.000s 167.663us 1 1 100.00
aes_stress 4.000s 353.740us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 77.002us 1 1 100.00
aes_config_error 4.000s 167.663us 1 1 100.00
aes_stress 4.000s 353.740us 1 1 100.00
back2back 2 2 100.00
aes_stress 4.000s 353.740us 1 1 100.00
aes_b2b 16.000s 288.651us 1 1 100.00
backpressure 1 1 100.00
aes_stress 4.000s 353.740us 1 1 100.00
multi_message 3 4 75.00
aes_smoke 2.000s 77.002us 1 1 100.00
aes_config_error 4.000s 167.663us 1 1 100.00
aes_stress 4.000s 353.740us 1 1 100.00
aes_alert_reset 26.000s 10014.771us 0 1 0.00
failure_test 2 3 66.67
aes_man_cfg_err 3.000s 148.400us 1 1 100.00
aes_config_error 4.000s 167.663us 1 1 100.00
aes_alert_reset 26.000s 10014.771us 0 1 0.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 155.223us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 7.000s 393.424us 1 1 100.00
reset_recovery 0 1 0.00
aes_alert_reset 26.000s 10014.771us 0 1 0.00
stress 1 1 100.00
aes_stress 4.000s 353.740us 1 1 100.00
sideload 2 2 100.00
aes_stress 4.000s 353.740us 1 1 100.00
aes_sideload 3.000s 75.918us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 81.053us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 75.000s 11205.445us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 2.000s 90.031us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 150.550us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 150.550us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 52.247us 1 1 100.00
aes_csr_rw 2.000s 56.551us 1 1 100.00
aes_csr_aliasing 3.000s 134.364us 1 1 100.00
aes_same_csr_outstanding 2.000s 70.980us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 52.247us 1 1 100.00
aes_csr_rw 2.000s 56.551us 1 1 100.00
aes_csr_aliasing 3.000s 134.364us 1 1 100.00
aes_same_csr_outstanding 2.000s 70.980us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 4.000s 411.618us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 15.000s 10051.587us 0 1 0.00
aes_control_fi 3.000s 57.372us 1 1 100.00
aes_cipher_fi 3.000s 53.616us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 1.000s 100.191us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 1.000s 100.191us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 1.000s 100.191us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 1.000s 100.191us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 193.558us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 4.000s 494.425us 1 1 100.00
aes_tl_intg_err 2.000s 311.265us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 311.265us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 0 1 0.00
aes_alert_reset 26.000s 10014.771us 0 1 0.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 100.191us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 100.191us 1 1 100.00
sec_cm_main_config_sparse 3 4 75.00
aes_smoke 2.000s 77.002us 1 1 100.00
aes_stress 4.000s 353.740us 1 1 100.00
aes_alert_reset 26.000s 10014.771us 0 1 0.00
aes_core_fi 3.000s 421.972us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 4.000s 167.663us 1 1 100.00
aes_stress 4.000s 353.740us 1 1 100.00
aes_core_fi 3.000s 421.972us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 100.191us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 58.987us 1 1 100.00
aes_stress 4.000s 353.740us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 4.000s 353.740us 1 1 100.00
aes_sideload 3.000s 75.918us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 58.987us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 58.987us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 58.987us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 58.987us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 58.987us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 4.000s 353.740us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 4.000s 353.740us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 15.000s 10051.587us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 15.000s 10051.587us 0 1 0.00
aes_control_fi 3.000s 57.372us 1 1 100.00
aes_cipher_fi 3.000s 53.616us 1 1 100.00
aes_ctr_fi 2.000s 60.298us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 15.000s 10051.587us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 15.000s 10051.587us 0 1 0.00
aes_control_fi 3.000s 57.372us 1 1 100.00
aes_cipher_fi 3.000s 53.616us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 3.000s 53.616us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 15.000s 10051.587us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 15.000s 10051.587us 0 1 0.00
aes_control_fi 3.000s 57.372us 1 1 100.00
aes_ctr_fi 2.000s 60.298us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 15.000s 10051.587us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 15.000s 10051.587us 0 1 0.00
aes_control_fi 3.000s 57.372us 1 1 100.00
aes_cipher_fi 3.000s 53.616us 1 1 100.00
aes_ctr_fi 2.000s 60.298us 1 1 100.00
sec_cm_main_fsm_global_esc 0 1 0.00
aes_alert_reset 26.000s 10014.771us 0 1 0.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 15.000s 10051.587us 0 1 0.00
aes_control_fi 3.000s 57.372us 1 1 100.00
aes_cipher_fi 3.000s 53.616us 1 1 100.00
aes_ctr_fi 2.000s 60.298us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 15.000s 10051.587us 0 1 0.00
aes_control_fi 3.000s 57.372us 1 1 100.00
aes_cipher_fi 3.000s 53.616us 1 1 100.00
aes_ctr_fi 2.000s 60.298us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 15.000s 10051.587us 0 1 0.00
aes_control_fi 3.000s 57.372us 1 1 100.00
aes_ctr_fi 2.000s 60.298us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 15.000s 10051.587us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 15.000s 10051.587us 0 1 0.00
aes_control_fi 3.000s 57.372us 1 1 100.00
aes_cipher_fi 3.000s 53.616us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 46.000s 8510.523us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:454) [aes_alert_reset_vseq] wait timeout occurred! 2 test runs
aes_alert_reset 26124970233927384159495991016380259271790751809495957454753810552367113948755 1533
UVM_INFO @ 10014771061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all 95475032339746238844681970517708375659169886336379940288613148499637559073753 130720
UVM_INFO @ 11205445495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [aes_fi_vseq] wait timeout occurred! 1 test run
aes_fi 35739945876353724604214988072853020088779360201884437395168891014662979945196 2330
UVM_INFO @ 10051587047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:76) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 1 test run
aes_stress_all_with_rand_reset 29173642959945294126704110776748149691868996318603513784310156183669109410867 1718
UVM_INFO @ 8510522922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---