Simulation Results: aes/unmasked

 
07/05/2026 15:30:24 DVSim: v1.34.0 sha: 9bbcf3f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.02 %
  • code
  • 89.73 %
  • assert
  • 97.73 %
  • func
  • 76.60 %
  • block
  • 89.43 %
  • line
  • 91.77 %
  • branch
  • 79.54 %
  • toggle
  • 97.99 %
  • FSM
  • 89.63 %
Validation stages
V1
100.00%
V2
94.12%
V2S
93.75%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 56.301us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 330.475us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 161.031us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 62.905us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 3.000s 336.022us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 372.981us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 81.048us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 62.905us 1 1 100.00
aes_csr_aliasing 2.000s 372.981us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 330.475us 1 1 100.00
aes_config_error 3.000s 136.433us 1 1 100.00
aes_stress 2.000s 64.442us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 330.475us 1 1 100.00
aes_config_error 3.000s 136.433us 1 1 100.00
aes_stress 2.000s 64.442us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 64.442us 1 1 100.00
aes_b2b 2.000s 126.540us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 64.442us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 3.000s 330.475us 1 1 100.00
aes_config_error 3.000s 136.433us 1 1 100.00
aes_stress 2.000s 64.442us 1 1 100.00
aes_alert_reset 3.000s 115.343us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 1.000s 75.652us 1 1 100.00
aes_config_error 3.000s 136.433us 1 1 100.00
aes_alert_reset 3.000s 115.343us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 61.662us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 3.000s 425.388us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 3.000s 115.343us 1 1 100.00
stress 1 1 100.00
aes_stress 2.000s 64.442us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 64.442us 1 1 100.00
aes_sideload 2.000s 68.907us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 124.736us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 33.000s 10137.311us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 2.000s 55.571us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 117.691us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 117.691us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 161.031us 1 1 100.00
aes_csr_rw 2.000s 62.905us 1 1 100.00
aes_csr_aliasing 2.000s 372.981us 1 1 100.00
aes_same_csr_outstanding 3.000s 159.393us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 161.031us 1 1 100.00
aes_csr_rw 2.000s 62.905us 1 1 100.00
aes_csr_aliasing 2.000s 372.981us 1 1 100.00
aes_same_csr_outstanding 3.000s 159.393us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 3.000s 544.927us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 9.000s 10092.669us 0 1 0.00
aes_control_fi 2.000s 51.567us 1 1 100.00
aes_cipher_fi 2.000s 49.852us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 83.810us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 83.810us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 83.810us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 83.810us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 263.853us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 4.000s 815.619us 1 1 100.00
aes_tl_intg_err 2.000s 236.530us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 236.530us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 3.000s 115.343us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 83.810us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 83.810us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 3.000s 330.475us 1 1 100.00
aes_stress 2.000s 64.442us 1 1 100.00
aes_alert_reset 3.000s 115.343us 1 1 100.00
aes_core_fi 3.000s 326.836us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 3.000s 136.433us 1 1 100.00
aes_stress 2.000s 64.442us 1 1 100.00
aes_core_fi 3.000s 326.836us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 83.810us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 109.848us 1 1 100.00
aes_stress 2.000s 64.442us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 64.442us 1 1 100.00
aes_sideload 2.000s 68.907us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 109.848us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 109.848us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 109.848us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 109.848us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 109.848us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 64.442us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 64.442us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 9.000s 10092.669us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 9.000s 10092.669us 0 1 0.00
aes_control_fi 2.000s 51.567us 1 1 100.00
aes_cipher_fi 2.000s 49.852us 1 1 100.00
aes_ctr_fi 2.000s 75.986us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 9.000s 10092.669us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 9.000s 10092.669us 0 1 0.00
aes_control_fi 2.000s 51.567us 1 1 100.00
aes_cipher_fi 2.000s 49.852us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 49.852us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 9.000s 10092.669us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 9.000s 10092.669us 0 1 0.00
aes_control_fi 2.000s 51.567us 1 1 100.00
aes_ctr_fi 2.000s 75.986us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 9.000s 10092.669us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 9.000s 10092.669us 0 1 0.00
aes_control_fi 2.000s 51.567us 1 1 100.00
aes_cipher_fi 2.000s 49.852us 1 1 100.00
aes_ctr_fi 2.000s 75.986us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 3.000s 115.343us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 9.000s 10092.669us 0 1 0.00
aes_control_fi 2.000s 51.567us 1 1 100.00
aes_cipher_fi 2.000s 49.852us 1 1 100.00
aes_ctr_fi 2.000s 75.986us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 9.000s 10092.669us 0 1 0.00
aes_control_fi 2.000s 51.567us 1 1 100.00
aes_cipher_fi 2.000s 49.852us 1 1 100.00
aes_ctr_fi 2.000s 75.986us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 9.000s 10092.669us 0 1 0.00
aes_control_fi 2.000s 51.567us 1 1 100.00
aes_ctr_fi 2.000s 75.986us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 9.000s 10092.669us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 9.000s 10092.669us 0 1 0.00
aes_control_fi 2.000s 51.567us 1 1 100.00
aes_cipher_fi 2.000s 49.852us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 15.000s 602.787us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:454) [aes_fi_vseq] wait timeout occurred! 1 test run
aes_fi 95971820618204539568807431870446066413580243656909500249256761630863213569647 1284
UVM_INFO @ 10092668623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [aes_alert_reset_vseq] wait timeout occurred! 1 test run
aes_stress_all 73361439714226327475515318527782892161482122648952216837654155565997788811391 26265
UVM_INFO @ 10137311270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:76) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 1 test run
aes_stress_all_with_rand_reset 31584090568006668050611351840449232238551234238229132030782648518642777414184 433
UVM_INFO @ 602786766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---