Simulation Results: alert_handler

 
07/05/2026 15:30:24 DVSim: v1.34.0 sha: 9bbcf3f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.72 %
  • code
  • 93.29 %
  • assert
  • 98.33 %
  • func
  • 80.54 %
  • line
  • 99.74 %
  • branch
  • 98.36 %
  • cond
  • 92.58 %
  • toggle
  • 93.49 %
  • FSM
  • 82.26 %
Validation stages
V1
100.00%
V2
94.74%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 24.600s 1270.679us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 4.330s 72.421us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 6.510s 524.843us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 312.700s 35699.834us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 49.320s 2212.836us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 6.240s 271.493us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 6.510s 524.843us 1 1 100.00
alert_handler_csr_aliasing 49.320s 2212.836us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 5.280s 114.083us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 7.040s 418.409us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 794.810s 40466.875us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 24.230s 1185.697us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 24.600s 1270.679us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 24.420s 2603.240us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 30.960s 1661.878us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 32.960s 1358.834us 0 1 0.00
lpg 2 2 100.00
alert_handler_lpg 393.390s 25779.197us 1 1 100.00
alert_handler_lpg_stub_clk 1195.350s 105601.668us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 174.890s 3720.527us 1 1 100.00
alert_handler_entropy_stress_test 1 1 100.00
alert_handler_entropy_stress 5.720s 293.298us 1 1 100.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 2.410s 74.988us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.220s 8.616us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 5.120s 266.705us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 5.120s 266.705us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 4.330s 72.421us 1 1 100.00
alert_handler_csr_rw 6.510s 524.843us 1 1 100.00
alert_handler_csr_aliasing 49.320s 2212.836us 1 1 100.00
alert_handler_same_csr_outstanding 14.720s 339.771us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 4.330s 72.421us 1 1 100.00
alert_handler_csr_rw 6.510s 524.843us 1 1 100.00
alert_handler_csr_aliasing 49.320s 2212.836us 1 1 100.00
alert_handler_same_csr_outstanding 14.720s 339.771us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 129.980s 2049.048us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 129.980s 2049.048us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 129.980s 2049.048us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 129.980s 2049.048us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 281.650s 12195.519us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 8.830s 897.721us 1 1 100.00
alert_handler_tl_intg_err 2.440s 46.574us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 2.440s 46.574us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 129.980s 2049.048us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 24.600s 1270.679us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 24.600s 1270.679us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 24.600s 1270.679us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 24.600s 1270.679us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 24.230s 1185.697us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 393.390s 25779.197us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 24.230s 1185.697us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 794.810s 40466.875us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 794.810s 40466.875us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 8.830s 897.721us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 8.830s 897.721us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 8.830s 897.721us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 8.830s 897.721us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 8.830s 897.721us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 8.830s 897.721us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 8.830s 897.721us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 8.830s 897.721us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 8.830s 897.721us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
alert_handler_stress_all_with_rand_reset 219.570s 5509.702us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state 1 test run
alert_handler_ping_timeout 31422690167446265211675002849651345723203114475171390468422636582821802215418 93
UVM_INFO @ 1358834497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---