Simulation Results

Simulation Results: chip

07/05/2026 15:30:24 DVSim: v1.34.0 sha: 9bbcf3f json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
76.35 %

code
84.91 %

assert
97.25 %

func
46.89 %

line
94.30 %

branch
93.06 %

cond
88.81 %

toggle
91.23 %

FSM
57.14 %

Validation stages

V1		100.00%
V2		78.78%
V2S		50.00%
V3		61.54%
unmapped		80.00%

18/18 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_example_tests				4	4	100.00
	chip_sw_example_flash	174.940s	3289.144us	1	1	100.00
	chip_sw_example_rom	59.020s	2113.362us	1	1	100.00
	chip_sw_example_manufacturer	200.220s	2766.459us	1	1	100.00
	chip_sw_example_concurrency	124.000s	2439.411us	1	1	100.00
csr_hw_reset				1	1	100.00
	chip_csr_hw_reset	312.670s	6525.129us	1	1	100.00
csr_rw				1	1	100.00
	chip_csr_rw	238.070s	3898.806us	1	1	100.00
csr_bit_bash				1	1	100.00
	chip_csr_bit_bash	2912.290s	42208.311us	1	1	100.00
csr_aliasing				1	1	100.00
	chip_csr_aliasing	4951.610s	31345.899us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	chip_csr_mem_rw_with_rand_reset	329.300s	7551.439us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	chip_csr_aliasing	4951.610s	31345.899us	1	1	100.00
	chip_csr_rw	238.070s	3898.806us	1	1	100.00
xbar_smoke				1	1	100.00
	xbar_smoke	6.850s	185.449us	1	1	100.00
chip_sw_gpio_out				1	1	100.00
	chip_sw_gpio	267.120s	4435.849us	1	1	100.00
chip_sw_gpio_in				1	1	100.00
	chip_sw_gpio	267.120s	4435.849us	1	1	100.00
chip_sw_gpio_irq				1	1	100.00
	chip_sw_gpio	267.120s	4435.849us	1	1	100.00
chip_sw_uart_tx_rx				1	1	100.00
	chip_sw_uart_tx_rx	369.290s	4109.232us	1	1	100.00
chip_sw_uart_rx_overflow				4	4	100.00
	chip_sw_uart_tx_rx	369.290s	4109.232us	1	1	100.00
	chip_sw_uart_tx_rx_idx1	347.550s	3985.811us	1	1	100.00
	chip_sw_uart_tx_rx_idx2	367.360s	4707.526us	1	1	100.00
	chip_sw_uart_tx_rx_idx3	418.140s	4291.580us	1	1	100.00
chip_sw_uart_baud_rate				1	1	100.00
	chip_sw_uart_rand_baudrate	331.250s	4225.972us	1	1	100.00
chip_sw_uart_tx_rx_alt_clk_freq				2	2	100.00
	chip_sw_uart_tx_rx_alt_clk_freq	1798.590s	13409.037us	1	1	100.00
	chip_sw_uart_tx_rx_alt_clk_freq_low_speed	976.340s	12950.339us	1	1	100.00

219/278 passed

78.78 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_pin_mux				1	1	100.00
	chip_padctrl_attributes	186.540s	4945.046us	1	1	100.00
chip_padctrl_attributes				1	1	100.00
	chip_padctrl_attributes	186.540s	4945.046us	1	1	100.00
chip_sw_sleep_pin_mio_dio_val				0	1	0.00
	chip_sw_sleep_pin_mio_dio_val	168.830s	2588.460us	0	1	0.00
chip_sw_sleep_pin_wake				1	1	100.00
	chip_sw_sleep_pin_wake	149.890s	3619.177us	1	1	100.00
chip_sw_sleep_pin_retention				1	1	100.00
	chip_sw_sleep_pin_retention	200.180s	4848.177us	1	1	100.00
chip_sw_tap_strap_sampling				4	4	100.00
	chip_tap_straps_dev	710.160s	11696.831us	1	1	100.00
	chip_tap_straps_testunlock0	94.530s	2505.047us	1	1	100.00
	chip_tap_straps_rma	220.450s	4176.025us	1	1	100.00
	chip_tap_straps_prod	94.090s	2534.553us	1	1	100.00
chip_sw_pattgen_ios				1	1	100.00
	chip_sw_pattgen_ios	159.330s	3197.799us	1	1	100.00
chip_sw_sleep_pwm_pulses				1	1	100.00
	chip_sw_sleep_pwm_pulses	808.830s	9940.620us	1	1	100.00
chip_sw_data_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	413.900s	5820.026us	1	1	100.00
chip_sw_instruction_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	413.900s	5820.026us	1	1	100.00
chip_sw_ast_clk_outputs				1	1	100.00
	chip_sw_ast_clk_outputs	662.860s	7775.188us	1	1	100.00
chip_sw_ast_clk_rst_inputs				0	1	0.00
	chip_sw_ast_clk_rst_inputs	895.590s	10681.944us	0	1	0.00
chip_sw_ast_sys_clk_jitter				10	10	100.00
	chip_sw_flash_ctrl_ops_jitter_en	369.500s	4457.349us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	609.400s	6443.111us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3516.520s	19456.972us	1	1	100.00
	chip_sw_aes_enc_jitter_en	134.170s	2745.952us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	620.790s	7395.153us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	159.690s	2571.888us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	1578.580s	13094.667us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	164.000s	3308.092us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	330.190s	3996.940us	1	1	100.00
	chip_sw_clkmgr_jitter	174.300s	3293.967us	1	1	100.00
chip_sw_ast_usb_clk_calib				1	1	100.00
	chip_sw_usb_ast_clk_calib	183.340s	3656.020us	1	1	100.00
chip_sw_sensor_ctrl_ast_alerts				2	2	100.00
	chip_sw_sensor_ctrl_alert	273.020s	3482.626us	1	1	100.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	215.110s	4576.264us	1	1	100.00
chip_sw_sensor_ctrl_ast_status				1	1	100.00
	chip_sw_sensor_ctrl_status	136.270s	3226.513us	1	1	100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup				1	1	100.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	215.110s	4576.264us	1	1	100.00
chip_sw_smoketest				17	17	100.00
	chip_sw_flash_scrambling_smoketest	145.070s	2435.578us	1	1	100.00
	chip_sw_aes_smoketest	154.440s	2681.161us	1	1	100.00
	chip_sw_aon_timer_smoketest	145.130s	2711.595us	1	1	100.00
	chip_sw_clkmgr_smoketest	164.470s	3247.486us	1	1	100.00
	chip_sw_csrng_smoketest	169.960s	2552.782us	1	1	100.00
	chip_sw_entropy_src_smoketest	894.140s	7216.927us	1	1	100.00
	chip_sw_gpio_smoketest	218.430s	3560.720us	1	1	100.00
	chip_sw_hmac_smoketest	236.610s	3433.764us	1	1	100.00
	chip_sw_kmac_smoketest	223.310s	2949.165us	1	1	100.00
	chip_sw_otbn_smoketest	775.000s	7202.584us	1	1	100.00
	chip_sw_pwrmgr_smoketest	274.470s	6376.482us	1	1	100.00
	chip_sw_pwrmgr_usbdev_smoketest	299.530s	5670.004us	1	1	100.00
	chip_sw_rv_plic_smoketest	188.420s	2838.048us	1	1	100.00
	chip_sw_rv_timer_smoketest	139.700s	2837.635us	1	1	100.00
	chip_sw_rstmgr_smoketest	151.960s	2816.189us	1	1	100.00
	chip_sw_sram_ctrl_smoketest	141.280s	3267.615us	1	1	100.00
	chip_sw_uart_smoketest	139.330s	2605.483us	1	1	100.00
chip_sw_otp_smoketest				1	1	100.00
	chip_sw_otp_ctrl_smoketest	134.880s	3319.594us	1	1	100.00
chip_sw_rom_functests				0	1	0.00
	rom_keymgr_functest	387.250s	5364.803us	0	1	0.00
chip_sw_boot				1	1	100.00
	chip_sw_uart_tx_rx_bootstrap	7817.010s	64097.143us	1	1	100.00
chip_sw_secure_boot				1	1	100.00
	rom_e2e_smoke	3204.580s	16010.346us	1	1	100.00
chip_sw_rom_raw_unlock				0	1	0.00
	rom_raw_unlock	106.451s	0.000us	0	1	0.00
chip_sw_power_idle_load				0	1	0.00
	chip_sw_power_idle_load	246.970s	3535.806us	0	1	0.00
chip_sw_power_sleep_load				0	1	0.00
	chip_sw_power_sleep_load	172.990s	3655.148us	0	1	0.00
chip_sw_exit_test_unlocked_bootstrap				1	1	100.00
	chip_sw_exit_test_unlocked_bootstrap	7407.240s	56865.690us	1	1	100.00
chip_sw_inject_scramble_seed				1	1	100.00
	chip_sw_inject_scramble_seed	7869.670s	58356.213us	1	1	100.00
tl_d_oob_addr_access				0	1	0.00
	chip_tl_errors	50.460s	2595.435us	0	1	0.00
tl_d_illegal_access				0	1	0.00
	chip_tl_errors	50.460s	2595.435us	0	1	0.00
tl_d_outstanding_access				4	4	100.00
	chip_csr_aliasing	4951.610s	31345.899us	1	1	100.00
	chip_same_csr_outstanding	2946.670s	28930.318us	1	1	100.00
	chip_csr_hw_reset	312.670s	6525.129us	1	1	100.00
	chip_csr_rw	238.070s	3898.806us	1	1	100.00
tl_d_partial_access				4	4	100.00
	chip_csr_aliasing	4951.610s	31345.899us	1	1	100.00
	chip_same_csr_outstanding	2946.670s	28930.318us	1	1	100.00
	chip_csr_hw_reset	312.670s	6525.129us	1	1	100.00
	chip_csr_rw	238.070s	3898.806us	1	1	100.00
xbar_base_random_sequence				1	1	100.00
	xbar_random	6.340s	158.865us	1	1	100.00
xbar_random_delay				6	6	100.00
	xbar_smoke_zero_delays	5.440s	49.643us	1	1	100.00
	xbar_smoke_large_delays	56.940s	8832.475us	1	1	100.00
	xbar_smoke_slow_rsp	43.320s	4322.703us	1	1	100.00
	xbar_random_zero_delays	33.540s	538.989us	1	1	100.00
	xbar_random_large_delays	161.020s	24738.929us	1	1	100.00
	xbar_random_slow_rsp	220.970s	23943.185us	1	1	100.00
xbar_unmapped_address				2	2	100.00
	xbar_unmapped_addr	18.790s	203.695us	1	1	100.00
	xbar_error_and_unmapped_addr	16.710s	541.028us	1	1	100.00
xbar_error_cases				2	2	100.00
	xbar_error_random	47.160s	1957.403us	1	1	100.00
	xbar_error_and_unmapped_addr	16.710s	541.028us	1	1	100.00
xbar_all_access_same_device				2	2	100.00
	xbar_access_same_device	32.180s	560.528us	1	1	100.00
	xbar_access_same_device_slow_rsp	141.670s	16327.128us	1	1	100.00
xbar_all_hosts_use_same_source_id				1	1	100.00
	xbar_same_source	54.320s	2492.622us	1	1	100.00
xbar_stress_all				2	2	100.00
	xbar_stress_all	216.410s	10366.330us	1	1	100.00
	xbar_stress_all_with_error	79.290s	3468.793us	1	1	100.00
xbar_stress_with_reset				2	2	100.00
	xbar_stress_all_with_rand_reset	411.730s	9435.844us	1	1	100.00
	xbar_stress_all_with_reset_error	28.460s	80.996us	1	1	100.00
rom_e2e_smoke				1	1	100.00
	rom_e2e_smoke	3204.580s	16010.346us	1	1	100.00
rom_e2e_shutdown_output				1	1	100.00
	rom_e2e_shutdown_output	2593.150s	26688.756us	1	1	100.00
rom_e2e_shutdown_exception_c				1	1	100.00
	rom_e2e_shutdown_exception_c	3091.970s	16724.408us	1	1	100.00
rom_e2e_boot_policy_valid				0	15	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	154.621s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_dev	9.316s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod	11.272s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod_end	11.393s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_rma	8.823s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	53.209s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_dev	24.815s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod	16.117s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	9.442s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_rma	14.446s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	140.168s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_dev	64.132s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod	33.077s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	32.080s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_rma	22.940s	0.000us	0	1	0.00
rom_e2e_sigverify_always				0	15	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	18.110s	10.360us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_dev	20.090s	10.400us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod	18.470s	10.280us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod_end	17.330s	10.100us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_rma	17.400s	10.240us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	16.570s	10.200us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_dev	17.500s	10.140us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod	18.170s	10.100us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	17.420s	10.100us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_rma	20.910s	10.220us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	20.230s	10.280us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_dev	18.180s	10.100us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod	17.320s	10.400us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	17.100s	10.300us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_rma	18.560s	10.120us	0	1	0.00
rom_e2e_asm_init				0	5	0.00
	rom_e2e_asm_init_test_unlocked0	131.085s	0.000us	0	1	0.00
	rom_e2e_asm_init_dev	110.941s	0.000us	0	1	0.00
	rom_e2e_asm_init_prod	102.382s	0.000us	0	1	0.00
	rom_e2e_asm_init_prod_end	55.803s	0.000us	0	1	0.00
	rom_e2e_asm_init_rma	36.635s	0.000us	0	1	0.00
rom_e2e_keymgr_init				3	3	100.00
	rom_e2e_keymgr_init_rom_ext_meas	5758.450s	31215.415us	1	1	100.00
	rom_e2e_keymgr_init_rom_ext_no_meas	5989.770s	29465.409us	1	1	100.00
	rom_e2e_keymgr_init_rom_ext_invalid_meas	5969.240s	30040.238us	1	1	100.00
rom_e2e_static_critical				1	1	100.00
	rom_e2e_static_critical	3144.320s	16487.193us	1	1	100.00
chip_sw_adc_ctrl_debug_cable_irq				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3246.850s	34681.220us	0	1	0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3246.850s	34681.220us	0	1	0.00
chip_sw_aes_enc				2	2	100.00
	chip_sw_aes_enc	194.930s	3669.395us	1	1	100.00
	chip_sw_aes_enc_jitter_en	134.170s	2745.952us	1	1	100.00
chip_sw_aes_entropy				1	1	100.00
	chip_sw_aes_entropy	168.280s	2721.333us	1	1	100.00
chip_sw_aes_idle				1	1	100.00
	chip_sw_aes_idle	144.790s	2983.339us	1	1	100.00
chip_sw_aes_sideload				1	1	100.00
	chip_sw_keymgr_sideload_aes	1165.270s	9866.199us	1	1	100.00
chip_sw_alert_handler_alerts				0	1	0.00
	chip_sw_alert_test	155.150s	2499.753us	0	1	0.00
chip_sw_alert_handler_escalations				1	1	100.00
	chip_sw_alert_handler_escalation	360.850s	4697.418us	1	1	100.00
chip_sw_all_escalation_resets				1	1	100.00
	chip_sw_all_escalation_resets	433.010s	5852.258us	1	1	100.00
chip_sw_alert_handler_irqs				3	3	100.00
	chip_plic_all_irqs_0	517.200s	5398.976us	1	1	100.00
	chip_plic_all_irqs_10	270.910s	3613.352us	1	1	100.00
	chip_plic_all_irqs_20	399.150s	4773.657us	1	1	100.00
chip_sw_alert_handler_entropy				1	1	100.00
	chip_sw_alert_handler_entropy	179.960s	3435.890us	1	1	100.00
chip_sw_alert_handler_crashdump				1	1	100.00
	chip_sw_rstmgr_alert_info	1225.670s	11299.467us	1	1	100.00
chip_sw_alert_handler_ping_timeout				1	1	100.00
	chip_sw_alert_handler_ping_timeout	251.730s	4384.148us	1	1	100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_alerts	124.510s	3128.023us	0	1	0.00
chip_sw_alert_handler_lpg_sleep_mode_pings				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_pings	14400.138s	0.000us	0	1	0.00
chip_sw_alert_handler_lpg_clock_off				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	889.070s	7052.304us	1	1	100.00
chip_sw_alert_handler_lpg_reset_toggle				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	1013.490s	7152.154us	1	1	100.00
chip_sw_alert_handler_ping_ok				1	1	100.00
	chip_sw_alert_handler_ping_ok	762.330s	7477.553us	1	1	100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep				1	1	100.00
	chip_sw_alert_handler_reverse_ping_in_deep_sleep	8131.450s	255485.957us	1	1	100.00
chip_sw_aon_timer_wakeup_irq				1	1	100.00
	chip_sw_aon_timer_irq	292.380s	3951.587us	1	1	100.00
chip_sw_aon_timer_sleep_wakeup				1	1	100.00
	chip_sw_pwrmgr_smoketest	274.470s	6376.482us	1	1	100.00
chip_sw_aon_timer_wdog_bark_irq				1	1	100.00
	chip_sw_aon_timer_irq	292.380s	3951.587us	1	1	100.00
chip_sw_aon_timer_wdog_bite_reset				0	1	0.00
	chip_sw_aon_timer_wdog_bite_reset	339.030s	6948.801us	0	1	0.00
chip_sw_aon_timer_sleep_wdog_bite_reset				0	1	0.00
	chip_sw_aon_timer_wdog_bite_reset	339.030s	6948.801us	0	1	0.00
chip_sw_aon_timer_sleep_wdog_sleep_pause				1	1	100.00
	chip_sw_aon_timer_sleep_wdog_sleep_pause	224.970s	6143.464us	1	1	100.00
chip_sw_aon_timer_wdog_lc_escalate				1	1	100.00
	chip_sw_aon_timer_wdog_lc_escalate	370.570s	5222.219us	1	1	100.00
chip_sw_clkmgr_idle_trans				4	4	100.00
	chip_sw_otbn_randomness	622.400s	6057.128us	1	1	100.00
	chip_sw_aes_idle	144.790s	2983.339us	1	1	100.00
	chip_sw_hmac_enc_idle	165.430s	2844.879us	1	1	100.00
	chip_sw_kmac_idle	182.490s	3450.211us	1	1	100.00
chip_sw_clkmgr_off_trans				4	4	100.00
	chip_sw_clkmgr_off_aes_trans	233.960s	4281.780us	1	1	100.00
	chip_sw_clkmgr_off_hmac_trans	235.260s	5011.091us	1	1	100.00
	chip_sw_clkmgr_off_kmac_trans	255.210s	4855.628us	1	1	100.00
	chip_sw_clkmgr_off_otbn_trans	344.700s	5363.089us	1	1	100.00
chip_sw_clkmgr_off_peri				1	1	100.00
	chip_sw_clkmgr_off_peri	910.160s	13112.375us	1	1	100.00
chip_sw_clkmgr_div				7	7	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	418.640s	4422.194us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	388.320s	5183.447us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	383.550s	3709.786us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	401.010s	5446.988us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	417.190s	4582.762us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	396.990s	4797.379us	1	1	100.00
	chip_sw_ast_clk_outputs	662.860s	7775.188us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_lc				1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	369.120s	6096.382us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_sw				2	2	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	383.550s	3709.786us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	401.010s	5446.988us	1	1	100.00
chip_sw_clkmgr_jitter				10	10	100.00
	chip_sw_flash_ctrl_ops_jitter_en	369.500s	4457.349us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	609.400s	6443.111us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3516.520s	19456.972us	1	1	100.00
	chip_sw_aes_enc_jitter_en	134.170s	2745.952us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	620.790s	7395.153us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	159.690s	2571.888us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	1578.580s	13094.667us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	164.000s	3308.092us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	330.190s	3996.940us	1	1	100.00
	chip_sw_clkmgr_jitter	174.300s	3293.967us	1	1	100.00
chip_sw_clkmgr_extended_range				11	11	100.00
	chip_sw_clkmgr_jitter_reduced_freq	173.270s	3144.588us	1	1	100.00
	chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	391.630s	5124.583us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en_reduced_freq	643.750s	7697.968us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	3810.370s	24726.380us	1	1	100.00
	chip_sw_aes_enc_jitter_en_reduced_freq	207.850s	4011.121us	1	1	100.00
	chip_sw_hmac_enc_jitter_en_reduced_freq	171.670s	2773.934us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	1417.610s	13927.882us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	197.870s	3550.361us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	366.070s	5777.193us	1	1	100.00
	chip_sw_flash_init_reduced_freq	1290.290s	23778.670us	1	1	100.00
	chip_sw_csrng_edn_concurrency_reduced_freq	2582.080s	19642.526us	1	1	100.00
chip_sw_clkmgr_deep_sleep_frequency				1	1	100.00
	chip_sw_ast_clk_outputs	662.860s	7775.188us	1	1	100.00
chip_sw_clkmgr_sleep_frequency				1	1	100.00
	chip_sw_clkmgr_sleep_frequency	346.390s	4467.501us	1	1	100.00
chip_sw_clkmgr_reset_frequency				1	1	100.00
	chip_sw_clkmgr_reset_frequency	256.530s	3772.341us	1	1	100.00
chip_sw_clkmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	433.010s	5852.258us	1	1	100.00
chip_sw_clkmgr_alert_handler_clock_enables				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	889.070s	7052.304us	1	1	100.00
chip_sw_csrng_edn_cmd				1	1	100.00
	chip_sw_entropy_src_csrng	2189.860s	23927.461us	1	1	100.00
chip_sw_csrng_fuse_en_sw_app_read				0	1	0.00
	chip_sw_csrng_fuse_en_sw_app_read_test	178.830s	3356.961us	0	1	0.00
chip_sw_csrng_lc_hw_debug_en				1	1	100.00
	chip_sw_csrng_lc_hw_debug_en_test	479.510s	7162.556us	1	1	100.00
chip_sw_csrng_known_answer_tests				1	1	100.00
	chip_sw_csrng_kat_test	196.160s	3071.662us	1	1	100.00
chip_sw_edn_entropy_reqs				3	3	100.00
	chip_sw_csrng_edn_concurrency	2932.990s	18429.935us	1	1	100.00
	chip_sw_entropy_src_ast_rng_req	125.370s	3160.172us	1	1	100.00
	chip_sw_edn_entropy_reqs	832.550s	7484.770us	1	1	100.00
chip_sw_entropy_src_ast_rng_req				1	1	100.00
	chip_sw_entropy_src_ast_rng_req	125.370s	3160.172us	1	1	100.00
chip_sw_entropy_src_csrng				1	1	100.00
	chip_sw_entropy_src_csrng	2189.860s	23927.461us	1	1	100.00
chip_sw_entropy_src_known_answer_tests				1	1	100.00
	chip_sw_entropy_src_kat_test	176.150s	2975.994us	1	1	100.00
chip_sw_flash_init				1	1	100.00
	chip_sw_flash_init	986.660s	16945.943us	1	1	100.00
chip_sw_flash_host_access				2	2	100.00
	chip_sw_flash_ctrl_access	540.680s	6136.154us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	609.400s	6443.111us	1	1	100.00
chip_sw_flash_ctrl_ops				2	2	100.00
	chip_sw_flash_ctrl_ops	367.550s	4017.922us	1	1	100.00
	chip_sw_flash_ctrl_ops_jitter_en	369.500s	4457.349us	1	1	100.00
chip_sw_flash_rma_unlocked				1	1	100.00
	chip_sw_flash_rma_unlocked	3494.510s	43415.036us	1	1	100.00
chip_sw_flash_scramble				1	1	100.00
	chip_sw_flash_init	986.660s	16945.943us	1	1	100.00
chip_sw_flash_idle_low_power				1	1	100.00
	chip_sw_flash_ctrl_idle_low_power	208.090s	3606.840us	1	1	100.00
chip_sw_flash_keymgr_seeds				1	1	100.00
	chip_sw_keymgr_key_derivation	1286.380s	9966.871us	1	1	100.00
chip_sw_flash_lc_creator_seed_sw_rw_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	174.610s	2864.067us	0	1	0.00
chip_sw_flash_creator_seed_wipe_on_rma				1	1	100.00
	chip_sw_flash_rma_unlocked	3494.510s	43415.036us	1	1	100.00
chip_sw_flash_lc_owner_seed_sw_rw_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	174.610s	2864.067us	0	1	0.00
chip_sw_flash_lc_iso_part_sw_rd_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	174.610s	2864.067us	0	1	0.00
chip_sw_flash_lc_iso_part_sw_wr_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	174.610s	2864.067us	0	1	0.00
chip_sw_flash_lc_seed_hw_rd_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	174.610s	2864.067us	0	1	0.00
chip_sw_flash_lc_escalate_en				1	1	100.00
	chip_sw_all_escalation_resets	433.010s	5852.258us	1	1	100.00
chip_sw_flash_prim_tl_access				1	1	100.00
	chip_prim_tl_access	267.660s	10393.116us	1	1	100.00
chip_sw_flash_ctrl_clock_freqs				1	1	100.00
	chip_sw_flash_ctrl_clock_freqs	500.110s	4938.375us	1	1	100.00
chip_sw_flash_ctrl_escalation_reset				1	1	100.00
	chip_sw_flash_crash_alert	405.210s	6132.808us	1	1	100.00
chip_sw_flash_ctrl_write_clear				1	1	100.00
	chip_sw_flash_crash_alert	405.210s	6132.808us	1	1	100.00
chip_sw_hmac_enc				2	2	100.00
	chip_sw_hmac_enc	169.600s	3220.089us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	159.690s	2571.888us	1	1	100.00
chip_sw_hmac_idle				1	1	100.00
	chip_sw_hmac_enc_idle	165.430s	2844.879us	1	1	100.00
chip_sw_hmac_all_configurations				1	1	100.00
	chip_sw_hmac_oneshot	585.390s	5381.353us	1	1	100.00
chip_sw_hmac_multistream_mode				1	1	100.00
	chip_sw_hmac_multistream	728.310s	5810.772us	1	1	100.00
chip_sw_i2c_host_tx_rx				3	3	100.00
	chip_sw_i2c_host_tx_rx	395.020s	5054.745us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx1	400.230s	5124.492us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx2	429.020s	5184.531us	1	1	100.00
chip_sw_i2c_device_tx_rx				1	1	100.00
	chip_sw_i2c_device_tx_rx	300.770s	4013.042us	1	1	100.00
chip_sw_keymgr_key_derivation				2	2	100.00
	chip_sw_keymgr_key_derivation	1286.380s	9966.871us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	1578.580s	13094.667us	1	1	100.00
chip_sw_keymgr_sideload_kmac				1	1	100.00
	chip_sw_keymgr_sideload_kmac	1237.350s	9437.978us	1	1	100.00
chip_sw_keymgr_sideload_aes				1	1	100.00
	chip_sw_keymgr_sideload_aes	1165.270s	9866.199us	1	1	100.00
chip_sw_keymgr_sideload_otbn				1	1	100.00
	chip_sw_keymgr_sideload_otbn	2853.130s	15101.650us	1	1	100.00
chip_sw_kmac_enc				3	3	100.00
	chip_sw_kmac_mode_cshake	200.550s	3312.064us	1	1	100.00
	chip_sw_kmac_mode_kmac	218.060s	3517.730us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	164.000s	3308.092us	1	1	100.00
chip_sw_kmac_app_keymgr				1	1	100.00
	chip_sw_keymgr_key_derivation	1286.380s	9966.871us	1	1	100.00
chip_sw_kmac_app_lc				1	1	100.00
	chip_sw_lc_ctrl_transition	397.210s	8175.532us	1	1	100.00
chip_sw_kmac_app_rom				1	1	100.00
	chip_sw_kmac_app_rom	158.770s	3404.031us	1	1	100.00
chip_sw_kmac_entropy				1	1	100.00
	chip_sw_kmac_entropy	1284.900s	9915.678us	1	1	100.00
chip_sw_kmac_idle				1	1	100.00
	chip_sw_kmac_idle	182.490s	3450.211us	1	1	100.00
chip_sw_lc_ctrl_alert_handler_escalation				1	1	100.00
	chip_sw_alert_handler_escalation	360.850s	4697.418us	1	1	100.00
chip_sw_lc_ctrl_jtag_access				3	3	100.00
	chip_tap_straps_dev	710.160s	11696.831us	1	1	100.00
	chip_tap_straps_rma	220.450s	4176.025us	1	1	100.00
	chip_tap_straps_prod	94.090s	2534.553us	1	1	100.00
chip_sw_lc_ctrl_otp_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	132.560s	3135.449us	1	1	100.00
chip_sw_lc_ctrl_init				1	1	100.00
	chip_sw_lc_ctrl_transition	397.210s	8175.532us	1	1	100.00
chip_sw_lc_ctrl_transitions				1	1	100.00
	chip_sw_lc_ctrl_transition	397.210s	8175.532us	1	1	100.00
chip_sw_lc_ctrl_kmac_req				1	1	100.00
	chip_sw_lc_ctrl_transition	397.210s	8175.532us	1	1	100.00
chip_sw_lc_ctrl_key_div				1	1	100.00
	chip_sw_keymgr_key_derivation_prod	1471.640s	11806.064us	1	1	100.00
chip_sw_lc_ctrl_broadcast				19	22	86.36
	chip_sw_flash_ctrl_lc_rw_en	174.610s	2864.067us	0	1	0.00
	chip_sw_flash_rma_unlocked	3494.510s	43415.036us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	226.030s	3752.089us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	645.030s	6563.680us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	493.120s	7268.233us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	587.340s	7884.991us	0	1	0.00
	chip_sw_lc_ctrl_transition	397.210s	8175.532us	1	1	100.00
	chip_sw_keymgr_key_derivation	1286.380s	9966.871us	1	1	100.00
	chip_sw_rom_ctrl_integrity_check	346.850s	8530.105us	1	1	100.00
	chip_sw_sram_ctrl_execution_main	489.670s	6693.676us	1	1	100.00
	chip_prim_tl_access	267.660s	10393.116us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	369.120s	6096.382us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	418.640s	4422.194us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	388.320s	5183.447us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	383.550s	3709.786us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	401.010s	5446.988us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	417.190s	4582.762us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	396.990s	4797.379us	1	1	100.00
	chip_tap_straps_dev	710.160s	11696.831us	1	1	100.00
	chip_tap_straps_rma	220.450s	4176.025us	1	1	100.00
	chip_tap_straps_prod	94.090s	2534.553us	1	1	100.00
	chip_rv_dm_lc_disabled	75.920s	3670.401us	0	1	0.00
chip_lc_scrap				4	4	100.00
	chip_sw_lc_ctrl_rma_to_scrap	157.080s	3238.389us	1	1	100.00
	chip_sw_lc_ctrl_raw_to_scrap	94.980s	3379.825us	1	1	100.00
	chip_sw_lc_ctrl_test_locked0_to_scrap	106.900s	3801.877us	1	1	100.00
	chip_sw_lc_ctrl_rand_to_scrap	188.780s	3825.957us	1	1	100.00
chip_lc_test_locked				1	2	50.00
	chip_sw_lc_walkthrough_testunlocks	1557.250s	32228.447us	1	1	100.00
	chip_rv_dm_lc_disabled	75.920s	3670.401us	0	1	0.00
chip_sw_lc_walkthrough				2	5	40.00
	chip_sw_lc_walkthrough_dev	609.240s	10294.891us	0	1	0.00
	chip_sw_lc_walkthrough_prod	697.810s	10974.337us	0	1	0.00
	chip_sw_lc_walkthrough_prodend	741.600s	10219.840us	1	1	100.00
	chip_sw_lc_walkthrough_rma	337.760s	5593.901us	0	1	0.00
	chip_sw_lc_walkthrough_testunlocks	1557.250s	32228.447us	1	1	100.00
chip_sw_lc_ctrl_volatile_raw_unlock				2	3	66.67
	chip_sw_lc_ctrl_volatile_raw_unlock	80.820s	2901.723us	1	1	100.00
	chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	57.380s	2122.549us	1	1	100.00
	rom_volatile_raw_unlock	99.891s	0.000us	0	1	0.00
chip_sw_otbn_op				2	2	100.00
	chip_sw_otbn_ecdsa_op_irq	3685.700s	17166.286us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3516.520s	19456.972us	1	1	100.00
chip_sw_otbn_rnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	622.400s	6057.128us	1	1	100.00
chip_sw_otbn_urnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	622.400s	6057.128us	1	1	100.00
chip_sw_otbn_idle				1	1	100.00
	chip_sw_otbn_randomness	622.400s	6057.128us	1	1	100.00
chip_sw_otbn_mem_scramble				1	1	100.00
	chip_sw_otbn_mem_scramble	310.320s	3550.762us	1	1	100.00
chip_otp_ctrl_init				1	1	100.00
	chip_sw_lc_ctrl_transition	397.210s	8175.532us	1	1	100.00
chip_sw_otp_ctrl_keys				5	5	100.00
	chip_sw_flash_init	986.660s	16945.943us	1	1	100.00
	chip_sw_otbn_mem_scramble	310.320s	3550.762us	1	1	100.00
	chip_sw_keymgr_key_derivation	1286.380s	9966.871us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	399.730s	5922.884us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	155.740s	3485.706us	1	1	100.00
chip_sw_otp_ctrl_entropy				5	5	100.00
	chip_sw_flash_init	986.660s	16945.943us	1	1	100.00
	chip_sw_otbn_mem_scramble	310.320s	3550.762us	1	1	100.00
	chip_sw_keymgr_key_derivation	1286.380s	9966.871us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	399.730s	5922.884us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	155.740s	3485.706us	1	1	100.00
chip_sw_otp_ctrl_program				1	1	100.00
	chip_sw_lc_ctrl_transition	397.210s	8175.532us	1	1	100.00
chip_sw_otp_ctrl_program_error				1	1	100.00
	chip_sw_lc_ctrl_program_error	290.820s	4588.966us	1	1	100.00
chip_sw_otp_ctrl_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	132.560s	3135.449us	1	1	100.00
chip_sw_otp_ctrl_lc_signals				5	6	83.33
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	226.030s	3752.089us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	645.030s	6563.680us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	493.120s	7268.233us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	587.340s	7884.991us	0	1	0.00
	chip_sw_lc_ctrl_transition	397.210s	8175.532us	1	1	100.00
	chip_prim_tl_access	267.660s	10393.116us	1	1	100.00
chip_sw_otp_prim_tl_access				1	1	100.00
	chip_prim_tl_access	267.660s	10393.116us	1	1	100.00
chip_sw_otp_ctrl_dai_lock				1	1	100.00
	chip_sw_otp_ctrl_dai_lock	950.630s	6864.226us	1	1	100.00
chip_sw_pwrmgr_external_full_reset				0	1	0.00
	chip_sw_pwrmgr_full_aon_reset	174.600s	6572.136us	0	1	0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_wake_ups	929.680s	27281.675us	1	1	100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_all_wake_ups	284.090s	7210.015us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_por_reset				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_por_reset	416.860s	8589.542us	1	1	100.00
chip_sw_pwrmgr_normal_sleep_por_reset				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_por_reset	425.360s	6736.450us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_all_wake_ups	939.990s	25264.829us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs				1	2	50.00
	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	915.100s	13907.065us	1	1	100.00
	chip_sw_aon_timer_wdog_bite_reset	339.030s	6948.801us	0	1	0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	811.740s	13135.171us	1	1	100.00
chip_sw_pwrmgr_wdog_reset				1	1	100.00
	chip_sw_pwrmgr_wdog_reset	333.010s	5542.351us	1	1	100.00
chip_sw_pwrmgr_aon_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_full_aon_reset	174.600s	6572.136us	0	1	0.00
chip_sw_pwrmgr_main_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_main_power_glitch_reset	237.580s	5213.187us	1	1	100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	2758.640s	36706.930us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	373.400s	8775.845us	1	1	100.00
chip_sw_pwrmgr_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_sleep_power_glitch_reset	152.730s	2881.697us	0	1	0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs				1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	1700.570s	24149.701us	1	1	100.00
chip_sw_pwrmgr_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	603.470s	7062.717us	1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	1005.870s	11059.599us	1	1	100.00
chip_sw_pwrmgr_b2b_sleep_reset_req				1	1	100.00
	chip_sw_pwrmgr_b2b_sleep_reset_req	1914.910s	25610.002us	1	1	100.00
chip_sw_pwrmgr_sleep_disabled				1	1	100.00
	chip_sw_pwrmgr_sleep_disabled	188.670s	3193.610us	1	1	100.00
chip_sw_pwrmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	433.010s	5852.258us	1	1	100.00
chip_sw_rom_access				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	346.850s	8530.105us	1	1	100.00
chip_sw_rom_ctrl_integrity_check				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	346.850s	8530.105us	1	1	100.00
chip_sw_rstmgr_non_sys_reset_info				4	4	100.00
	chip_sw_pwrmgr_all_reset_reqs	1005.870s	11059.599us	1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	1700.570s	24149.701us	1	1	100.00
	chip_sw_pwrmgr_wdog_reset	333.010s	5542.351us	1	1	100.00
	chip_sw_pwrmgr_smoketest	274.470s	6376.482us	1	1	100.00
chip_sw_rstmgr_sys_reset_info				1	1	100.00
	chip_rv_dm_ndm_reset_req	334.050s	3962.943us	1	1	100.00
chip_sw_rstmgr_cpu_info				1	1	100.00
	chip_sw_rstmgr_cpu_info	341.370s	5219.336us	1	1	100.00
chip_sw_rstmgr_sw_req_reset				1	1	100.00
	chip_sw_rstmgr_sw_req	240.090s	4116.711us	1	1	100.00
chip_sw_rstmgr_alert_info				1	1	100.00
	chip_sw_rstmgr_alert_info	1225.670s	11299.467us	1	1	100.00
chip_sw_rstmgr_sw_rst				1	1	100.00
	chip_sw_rstmgr_sw_rst	178.270s	3020.786us	1	1	100.00
chip_sw_rstmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	433.010s	5852.258us	1	1	100.00
chip_sw_rstmgr_alert_handler_reset_enables				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	1013.490s	7152.154us	1	1	100.00
chip_sw_nmi_irq				1	1	100.00
	chip_sw_rv_core_ibex_nmi_irq	515.500s	4958.615us	1	1	100.00
chip_sw_rv_core_ibex_rnd				1	1	100.00
	chip_sw_rv_core_ibex_rnd	490.300s	5511.655us	1	1	100.00
chip_sw_rv_core_ibex_address_translation				1	1	100.00
	chip_sw_rv_core_ibex_address_translation	143.430s	3249.593us	1	1	100.00
chip_sw_rv_core_ibex_icache_scrambled_access				1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	155.740s	3485.706us	1	1	100.00
chip_sw_rv_core_ibex_fault_dump				1	1	100.00
	chip_sw_rstmgr_cpu_info	341.370s	5219.336us	1	1	100.00
chip_sw_rv_core_ibex_double_fault				1	1	100.00
	chip_sw_rstmgr_cpu_info	341.370s	5219.336us	1	1	100.00
chip_jtag_csr_rw				1	1	100.00
	chip_jtag_csr_rw	1177.010s	19440.396us	1	1	100.00
chip_jtag_mem_access				1	1	100.00
	chip_jtag_mem_access	1041.380s	14275.653us	1	1	100.00
chip_rv_dm_ndm_reset_req				1	1	100.00
	chip_rv_dm_ndm_reset_req	334.050s	3962.943us	1	1	100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted				0	1	0.00
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	165.700s	2983.666us	0	1	0.00
chip_rv_dm_access_after_wakeup				1	1	100.00
	chip_sw_rv_dm_access_after_wakeup	271.430s	6201.152us	1	1	100.00
chip_sw_rv_dm_jtag_tap_sel				1	1	100.00
	chip_tap_straps_rma	220.450s	4176.025us	1	1	100.00
chip_rv_dm_lc_disabled				0	1	0.00
	chip_rv_dm_lc_disabled	75.920s	3670.401us	0	1	0.00
chip_sw_plic_all_irqs				3	3	100.00
	chip_plic_all_irqs_0	517.200s	5398.976us	1	1	100.00
	chip_plic_all_irqs_10	270.910s	3613.352us	1	1	100.00
	chip_plic_all_irqs_20	399.150s	4773.657us	1	1	100.00
chip_sw_plic_sw_irq				1	1	100.00
	chip_sw_plic_sw_irq	165.400s	2714.478us	1	1	100.00
chip_sw_timer				1	1	100.00
	chip_sw_rv_timer_irq	140.540s	3248.235us	1	1	100.00
chip_sw_spi_device_flash_mode				1	1	100.00
	rom_e2e_smoke	3204.580s	16010.346us	1	1	100.00
chip_sw_spi_device_pass_through				1	1	100.00
	chip_sw_spi_device_pass_through	352.680s	5559.437us	1	1	100.00
chip_sw_spi_device_pass_through_collision				0	1	0.00
	chip_sw_spi_device_pass_through_collision	206.080s	3145.350us	0	1	0.00
chip_sw_spi_device_tpm				1	1	100.00
	chip_sw_spi_device_tpm	226.050s	3124.993us	1	1	100.00
chip_sw_spi_host_tx_rx				1	1	100.00
	chip_sw_spi_host_tx_rx	149.500s	3008.502us	1	1	100.00
chip_sw_sram_scrambled_access				2	2	100.00
	chip_sw_sram_ctrl_scrambled_access	399.730s	5922.884us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	330.190s	3996.940us	1	1	100.00
chip_sw_sleep_sram_ret_contents				2	2	100.00
	chip_sw_sleep_sram_ret_contents_no_scramble	357.390s	7298.414us	1	1	100.00
	chip_sw_sleep_sram_ret_contents_scramble	543.830s	8625.132us	1	1	100.00
chip_sw_sram_execution				1	1	100.00
	chip_sw_sram_ctrl_execution_main	489.670s	6693.676us	1	1	100.00
chip_sw_sram_lc_escalation				2	2	100.00
	chip_sw_all_escalation_resets	433.010s	5852.258us	1	1	100.00
	chip_sw_data_integrity_escalation	413.900s	5820.026us	1	1	100.00
chip_sw_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	603.470s	7062.717us	1	1	100.00
	chip_sw_sysrst_ctrl_reset	1149.500s	24334.246us	1	1	100.00
chip_sw_sysrst_ctrl_inputs				1	1	100.00
	chip_sw_sysrst_ctrl_inputs	192.910s	3169.819us	1	1	100.00
chip_sw_sysrst_ctrl_outputs				1	1	100.00
	chip_sw_sysrst_ctrl_outputs	220.330s	4213.609us	1	1	100.00
chip_sw_sysrst_ctrl_in_irq				1	1	100.00
	chip_sw_sysrst_ctrl_in_irq	340.320s	4566.411us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_wakeup				1	1	100.00
	chip_sw_sysrst_ctrl_reset	1149.500s	24334.246us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_reset				1	1	100.00
	chip_sw_sysrst_ctrl_reset	1149.500s	24334.246us	1	1	100.00
chip_sw_sysrst_ctrl_ec_rst_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	2584.160s	20832.563us	1	1	100.00
chip_sw_sysrst_ctrl_flash_wp_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	2584.160s	20832.563us	1	1	100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup				1	2	50.00
	chip_sw_sysrst_ctrl_ulp_z3_wakeup	224.790s	5928.799us	1	1	100.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3246.850s	34681.220us	0	1	0.00
chip_sw_usbdev_vbus				1	1	100.00
	chip_sw_usbdev_vbus	150.300s	2590.914us	1	1	100.00
chip_sw_usbdev_pullup				1	1	100.00
	chip_sw_usbdev_pullup	153.300s	2326.708us	1	1	100.00
chip_sw_usbdev_aon_pullup				1	1	100.00
	chip_sw_usbdev_aon_pullup	287.650s	4191.483us	1	1	100.00
chip_sw_usbdev_setup_rx				1	1	100.00
	chip_sw_usbdev_setuprx	334.140s	3945.994us	1	1	100.00
chip_sw_usbdev_config_host				1	1	100.00
	chip_sw_usbdev_config_host	1000.970s	7787.618us	1	1	100.00
chip_sw_usbdev_pincfg				1	1	100.00
	chip_sw_usbdev_pincfg	4897.750s	32004.019us	1	1	100.00
chip_sw_usbdev_tx_rx				1	1	100.00
	chip_sw_usbdev_dpi	1891.310s	12120.651us	1	1	100.00
chip_sw_usbdev_toggle_restore				1	1	100.00
	chip_sw_usbdev_toggle_restore	120.280s	2378.574us	1	1	100.00

V2S

1/2 passed

50.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_aes_masking_off				1	1	100.00
	chip_sw_aes_masking_off	219.100s	2802.809us	1	1	100.00
chip_sw_rv_core_ibex_lockstep_glitch				0	1	0.00
	chip_sw_rv_core_ibex_lockstep_glitch	95.450s	2119.173us	0	1	0.00

16/26 passed

61.54 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_coremark				1	1	100.00
	chip_sw_coremark	9832.230s	71469.040us	1	1	100.00
chip_sw_power_max_load				1	1	100.00
	chip_sw_power_virus	1002.410s	6753.212us	1	1	100.00
rom_e2e_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	178.890s	4832.795us	0	1	0.00
	rom_e2e_jtag_debug_dev	212.460s	3937.290us	0	1	0.00
	rom_e2e_jtag_debug_rma	208.250s	5127.104us	0	1	0.00
rom_e2e_jtag_inject				0	3	0.00
	rom_e2e_jtag_inject_test_unlocked0	56.170s	2726.632us	0	1	0.00
	rom_e2e_jtag_inject_dev	69.170s	2907.816us	0	1	0.00
	rom_e2e_jtag_inject_rma	84.210s	2553.594us	0	1	0.00
rom_e2e_self_hash				0	1	0.00
	rom_e2e_self_hash	147.050s	0.000us	0	1	0.00
chip_sw_clkmgr_jitter_cycle_measurements				0	1	0.00
	chip_sw_clkmgr_jitter_frequency	281.740s	3680.271us	0	1	0.00
chip_sw_edn_boot_mode				1	1	100.00
	chip_sw_edn_boot_mode	326.950s	2715.864us	1	1	100.00
chip_sw_edn_auto_mode				1	1	100.00
	chip_sw_edn_auto_mode	560.270s	4148.894us	1	1	100.00
chip_sw_edn_sw_mode				1	1	100.00
	chip_sw_edn_sw_mode	804.280s	6798.427us	1	1	100.00
chip_sw_edn_kat				1	1	100.00
	chip_sw_edn_kat	242.150s	2707.627us	1	1	100.00
chip_sw_flash_memory_protection				1	1	100.00
	chip_sw_flash_ctrl_mem_protection	633.790s	4983.912us	1	1	100.00
chip_sw_otp_ctrl_vendor_test_csr_access				0	1	0.00
	chip_sw_otp_ctrl_vendor_test_csr_access	71.810s	2453.480us	0	1	0.00
chip_sw_otp_ctrl_escalation				0	1	0.00
	chip_sw_otp_ctrl_escalation	168.160s	2800.636us	0	1	0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up				1	1	100.00
	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	219.150s	5650.683us	1	1	100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active				1	1	100.00
	chip_sw_pwrmgr_usb_clk_disabled_when_active	315.000s	4437.279us	1	1	100.00
chip_sw_all_resets				1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	1005.870s	11059.599us	1	1	100.00
chip_rv_dm_perform_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	178.890s	4832.795us	0	1	0.00
	rom_e2e_jtag_debug_dev	212.460s	3937.290us	0	1	0.00
	rom_e2e_jtag_debug_rma	208.250s	5127.104us	0	1	0.00
chip_sw_rv_dm_access_after_hw_reset				1	1	100.00
	chip_sw_rv_dm_access_after_escalation_reset	337.170s	6388.531us	1	1	100.00
chip_sw_plic_alerts				1	1	100.00
	chip_sw_all_escalation_resets	433.010s	5852.258us	1	1	100.00
tick_configuration				1	1	100.00
	chip_sw_rv_timer_systick_test	5797.690s	38549.437us	1	1	100.00
counter_wrap				1	1	100.00
	chip_sw_rv_timer_systick_test	5797.690s	38549.437us	1	1	100.00
chip_sw_spi_device_output_when_disabled_or_sleeping				1	1	100.00
	chip_sw_spi_device_pinmux_sleep_retention	188.040s	3783.871us	1	1	100.00
chip_sw_uart_watermarks				1	1	100.00
	chip_sw_uart_tx_rx	369.290s	4109.232us	1	1	100.00
chip_sw_usbdev_stream				1	1	100.00
	chip_sw_usbdev_stream	3153.080s	18638.095us	1	1	100.00

unmapped

8/10 passed

80.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				8	10	80.00
	chip_sival_flash_info_access	228.480s	2733.088us	1	1	100.00
	chip_sw_rstmgr_rst_cnsty_escalation	437.700s	6071.296us	1	1	100.00
	chip_sw_otp_ctrl_rot_auth_config	5.110s	0.000us	0	1	0.00
	chip_sw_otp_ctrl_ecc_error_vendor_test	184.520s	2688.412us	1	1	100.00
	chip_sw_otp_ctrl_descrambling	155.230s	2994.594us	1	1	100.00
	chip_sw_pwrmgr_lowpower_cancel	251.060s	4126.343us	1	1	100.00
	chip_sw_pwrmgr_sleep_wake_5_bug	7.846s	0.000us	0	1	0.00
	chip_sw_flash_ctrl_write_clear	185.670s	3240.371us	1	1	100.00
	ate_bootstrap_flash_erase	6519.770s	44866.128us	1	1	100.00
	ate_bootstrap_disjoint	10102.680s	84884.719us	1	1	100.00

Error Messages

	Test	seed	line	log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']				24 test runs
	chip_sw_pwrmgr_sleep_wake_5_bug	11783895973460934298071925072646781240134408388236310572764794755104094754939	None	---- STDOUT ---- ---- STDERR ---- WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	95533992011128828547488843284421254660904535675382182600939154801810595935340	None	Another command (pid=600282) is running. Waiting for it to complete on the server (server_pid=236578)... Another command (pid=589276) is running. Waiting for it to complete on the server (server_pid=236578)... Another command (pid=613326) is running. Waiting for it to complete on the server (server_pid=236578)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_dev	82245778930323455100760944658331935762094220797950065956393782335759083841750	None	Waiting for it to complete... Another command (pid=628412) is running. Waiting for it to complete on the server (server_pid=236578)... Another command (pid=620295) is running. Waiting for it to complete on the server (server_pid=236578)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_prod	18226239873666377480202630665880878952576125101970124238018422641223191645460	None	Another command (pid=631742) is running. Waiting for it to complete on the server (server_pid=236578)... Another command (pid=630785) is running. Waiting for it to complete on the server (server_pid=236578)... Another command (pid=634697) is running. Waiting for it to complete on the server (server_pid=236578)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_prod_end	58754551160224562481621757203063008603855515192068572223295962338531217328138	None	Another command (pid=634697) is running. Waiting for it to complete on the server (server_pid=236578)... Another command (pid=628555) is running. Waiting for it to complete on the server (server_pid=236578)... Another command (pid=630000) is running. Waiting for it to complete on the server (server_pid=236578)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_rma	63805691568915121770400143050980196546710605527721468742126887856656145031978	None	---- STDERR ---- Another command (pid=620295) is running. Waiting for it to complete on the server (server_pid=236578)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	88137729157291626332720843326420014405766984943664325876683745598308964264717	None	---- STDERR ---- Another command (pid=354449) is running. Waiting for it to complete on the server (server_pid=236578)... Another command (pid=396762) is running. Waiting for it to complete on the server (server_pid=236578)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_dev	77932575761196992886224061580371298813667097792982812766287922287461112528456	None	Another command (pid=580187) is running. Waiting for it to complete on the server (server_pid=236578)... Another command (pid=576629) is running. Waiting for it to complete on the server (server_pid=236578)... Another command (pid=582218) is running. Waiting for it to complete on the server (server_pid=236578)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_prod	73155216560442826823928687052437140915147486345186271337117371547563527021560	None	Another command (pid=390457) is running. Waiting for it to complete on the server (server_pid=236578)... Another command (pid=551744) is running. Waiting for it to complete on the server (server_pid=236578)... Another command (pid=583436) is running. Waiting for it to complete on the server (server_pid=236578)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	48728146251933576085238150415269467403297585026034839307426139270078749258624	None	Another command (pid=613326) is running. Waiting for it to complete on the server (server_pid=236578)... Another command (pid=607873) is running. Waiting for it to complete on the server (server_pid=236578)... Another command (pid=608192) is running. Waiting for it to complete on the server (server_pid=236578)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_rma	115684582013087913517705094008109053650889989580862621398331121166737968823414	None	Another command (pid=631742) is running. Waiting for it to complete on the server (server_pid=236578)... Another command (pid=630785) is running. Waiting for it to complete on the server (server_pid=236578)... Another command (pid=634697) is running. Waiting for it to complete on the server (server_pid=236578)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	35912662459833978889724902871819562498137680399031734665766694010917810308344	None	Another command (pid=534560) is running. Waiting for it to complete on the server (server_pid=236578)... Another command (pid=424372) is running. Waiting for it to complete on the server (server_pid=236578)... Another command (pid=556637) is running. Waiting for it to complete on the server (server_pid=236578)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_dev	48494375124977412493930667686605031988394433701024512124681274271397424906310	None	Another command (pid=653607) is running. Waiting for it to complete on the server (server_pid=236578)... Another command (pid=650772) is running. Waiting for it to complete on the server (server_pid=236578)... Another command (pid=658722) is running. Waiting for it to complete on the server (server_pid=236578)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_prod	75785742730440574079446698051119322701231127063286728380370443955521628644928	None	Another command (pid=390457) is running. Waiting for it to complete on the server (server_pid=236578)... Another command (pid=583436) is running. Waiting for it to complete on the server (server_pid=236578)... Another command (pid=600282) is running. Waiting for it to complete on the server (server_pid=236578)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	92349012742571641346333657487292448865251924330883591377389050415815352006153	None	Another command (pid=390457) is running. Waiting for it to complete on the server (server_pid=236578)... Another command (pid=551744) is running. Waiting for it to complete on the server (server_pid=236578)... Another command (pid=583436) is running. Waiting for it to complete on the server (server_pid=236578)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_rma	102974885895099086658652631367727270398250688923572515743883136000522611025980	None	Another command (pid=580575) is running. Waiting for it to complete on the server (server_pid=236578)... Another command (pid=420745) is running. Waiting for it to complete on the server (server_pid=236578)... Another command (pid=581180) is running. Waiting for it to complete on the server (server_pid=236578)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_test_unlocked0	56879263327519221449655182892166093189759856913623355095257318200734631320788	None	Another command (pid=445746) is running. Waiting for it to complete on the server (server_pid=236578)... Another command (pid=446101) is running. Waiting for it to complete on the server (server_pid=236578)... Another command (pid=363886) is running. Waiting for it to complete on the server (server_pid=236578)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_dev	49862723193291609745332483443197304533654705491502168792609579898789734044536	None	Another command (pid=430407) is running. Waiting for it to complete on the server (server_pid=236578)... Another command (pid=614807) is running. Waiting for it to complete on the server (server_pid=236578)... Another command (pid=575423) is running. Waiting for it to complete on the server (server_pid=236578)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_prod	115266791567984778190424216983581082719127069601599203742303922162939127319650	None	Another command (pid=551744) is running. Waiting for it to complete on the server (server_pid=236578)... Another command (pid=583436) is running. Waiting for it to complete on the server (server_pid=236578)... Another command (pid=581661) is running. Waiting for it to complete on the server (server_pid=236578)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_prod_end	28030402317874399408054580589595596751718360605001901123054494352813828291327	None	Another command (pid=542838) is running. Waiting for it to complete on the server (server_pid=236578)... Another command (pid=422707) is running. Waiting for it to complete on the server (server_pid=236578)... Another command (pid=401944) is running. Waiting for it to complete on the server (server_pid=236578)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_rma	101291529789406520543777064054846523781093035023042483340484792843753656858372	None	Another command (pid=600701) is running. Waiting for it to complete on the server (server_pid=236578)... Another command (pid=597052) is running. Waiting for it to complete on the server (server_pid=236578)... Another command (pid=390457) is running. Waiting for it to complete on the server (server_pid=236578)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_volatile_raw_unlock	113147463696586647070964031684601025981220073946159682565608213874196824848519	None	Another command (pid=445281) is running. Waiting for it to complete on the server (server_pid=236578)... Another command (pid=446101) is running. Waiting for it to complete on the server (server_pid=236578)... Another command (pid=363886) is running. Waiting for it to complete on the server (server_pid=236578)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_raw_unlock	3304009987542668563879666226305348304010880249262980795609936475630105083975	None	Another command (pid=537953) is running. Waiting for it to complete on the server (server_pid=236578)... Another command (pid=542838) is running. Waiting for it to complete on the server (server_pid=236578)... Another command (pid=422707) is running. Waiting for it to complete on the server (server_pid=236578)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_self_hash	93031840831441594081875924604734550444398893769502274723713335576087869972981	None	Another command (pid=598308) is running. Waiting for it to complete on the server (server_pid=236578)... Another command (pid=600701) is running. Waiting for it to complete on the server (server_pid=236578)... Another command (pid=597052) is running. Waiting for it to complete on the server (server_pid=236578)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Error-[NOA] Null object access				7 test runs
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	14572981468475128845490703630644824129333062773175734535219586261702432165477	327	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_debug_test_unlocked0	39018647078491561931676053742209886791251038731044467264888737393857739431610	319	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_debug_dev	82371432543210696573261280128203236083023007887460738451717247957626007990128	319	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_debug_rma	32152360324358110787688775942901416639393084105661362638559402662113401326179	319	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_test_unlocked0	81609805130746139764853324526530995840746641458736024604293190672424115131396	305	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_dev	103862379686643118960039340200468886366020013061737937437501813637440090608411	305	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_rma	36529577739924939397683695616439692141912364050543719725248113296590965966448	307	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_.signed..scr.vmem could not be opened for r mode				6 test runs
	rom_e2e_sigverify_always_a_bad_b_bad_prod	9931310880296348348779949094051674151926541333879063528857778193663060224620	368	UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_bad_prod_end	82764435212129190678054100448308032554979751465835302801694439867312281595063	368	UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_bad_rma	41786198637508765768138841745278626785953198977308984678719192365637341543598	364	UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_prod	34391484103398882357927966411031332773099070350602972284999408136474088878788	328	UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	8703398790769912030193900799262869057536426834605010247740010514224347679159	328	UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_rma	75122259301485853438913738293139482047421675684242377044954970858448265178076	327	UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				3 test runs
	chip_sw_lc_walkthrough_dev	12487009895198476478858819076222490709121848135672939984385315187696751131095	369	UVM_INFO @ 10294.891008 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_prod	98302068568819813261819708413598875925967838067799104332965469576800335262224	369	UVM_INFO @ 10974.337260 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_rma	24540873669679577676454849982231591272926843998897020535154479675210795516815	341	UVM_INFO @ 5593.900580 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_.signed..scr.vmem could not be opened for r mode				3 test runs
	rom_e2e_sigverify_always_a_nothing_b_bad_prod	101312846508050113079013992318078335810678398383723376685103109539157011893380	328	UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	42363088314526601873933488326429431054677333016184860209643826936224268355452	328	UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_nothing_b_bad_rma	19938435104431537229642367433033822009434901368631792991462315612772761297480	328	UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'				2 test runs
	chip_sw_otp_ctrl_escalation	77808670332446395269999748511129627240505846155899895331901273595290491532286	316	UVM_ERROR @ 2800.636352 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A UVM_INFO @ 2800.636352 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_csrng_fuse_en_sw_app_read_test	18750289702379154882879567202419534639716599567275551238973308155308225300392	312	UVM_ERROR @ 3356.960712 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A UVM_INFO @ 3356.960712 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_.signed..scr.vmem could not be opened for r mode				2 test runs
	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	23980468461848252515708696987358625785902335463312531722624680620385663733839	362	UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	64605926881176563539409285157311066937028210601990427501548208484592129993815	326	UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_.signed..scr.vmem could not be opened for r mode				2 test runs
	rom_e2e_sigverify_always_a_bad_b_bad_dev	23061785083987210257145673513201644495676606019058548314768759008495870871092	368	UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_dev	111888275088603254275727429172431944908267370574862725672758338984786392228344	327	UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [] vs xz [z]) for MIO[*]				1 test run
	chip_sw_sleep_pin_mio_dio_val	67803044715153045055920260710699542877487840597120764303192237132066031809183	451	UVM_INFO @ 2588.460000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty				1 test run
	chip_sw_spi_device_pass_through_collision	66275227132337392391252624244080600182561177127712084027977186746880337874557	320	UVM_INFO @ 3145.350020 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				1 test run
	chip_sw_flash_ctrl_lc_rw_en	55814205918374588382116166912790214336056791196068960057186117118925211565670	309	UVM_INFO @ 2864.066599 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *				1 test run
	chip_sw_otp_ctrl_lc_signals_rma	28851040851912276056272210134029806739998420017621442957343376178502024571252	342	UVM_INFO @ 7884.990848 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_otp_ctrl_vendor_test_csr_access_vseq.sv:81) [chip_sw_otp_ctrl_vendor_test_csr_access_vseq] Check failed otp_vendor_test_status == cfg.otp_test_status (* [] vs [*])				1 test run
	chip_sw_otp_ctrl_vendor_test_csr_access	95660324836330555134368852461968055081560691784945747754255630755124563535238	301	UVM_INFO @ 2453.480135 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode				1 test run
	chip_sw_otp_ctrl_rot_auth_config	114885833047627768596517693189994861496260365198599175652304782759315071326712	282	UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))'				1 test run
	chip_sw_pwrmgr_full_aon_reset	61813604661971263575432489408586537988405737068673162091000032966033620160162	322	UVM_ERROR @ 6572.136414 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A UVM_INFO @ 6572.136414 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))'				1 test run
	chip_sw_pwrmgr_sleep_power_glitch_reset	62225664230206523857976044934722461700362380216985112950194958914687631910687	313	UVM_ERROR @ 2881.696950 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A UVM_INFO @ 2881.696950 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))'				1 test run
	chip_sw_aon_timer_wdog_bite_reset	35428163093467513111321701911515625328041800453538758389847936692937085825022	319	UVM_ERROR @ 6948.801000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 6948.801000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns				1 test run
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	39003530986014449960032008030813454524673779137932033983271597674650351170327	332	UVM_INFO @ 34681.219686 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:352)] CHECK-fail: Expect alert *!				1 test run
	chip_sw_alert_test	41834989105230017271071467134349060444170472361706446116347507752483245516768	307	UVM_INFO @ 2499.752922 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)				1 test run
	chip_sw_alert_handler_lpg_sleep_mode_alerts	33548164957442903674693628168347578190326440822832362759476159182427788554337	308	UVM_INFO @ 3128.023324 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				1 test run
	chip_sw_alert_handler_lpg_sleep_mode_pings	53323355558772748702249549279324727326327926227555053498363808323010418327137	None
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted , but saw ).				1 test run
	chip_tl_errors	2679139401864293236331805761787227295140627287525938260949023465508109041049	217	TL item was: req: (cip_tl_seq_item@34357) { a_addr: 'h10438 a_data: 'h877e5cf0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'ha a_opcode: 'h4 a_user: 'h1bd40 d_param: 'h0 d_source: 'ha d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 } Reasons for predicted error: '{"Fetch from CSR"} . UVM_INFO @ 2595.435143 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				1 test run
	chip_sw_clkmgr_jitter_frequency	24484439180390751958649089491160244855639209305748481529288233554286891931163	343	UVM_INFO @ 3680.271367 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:649) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [] vs []) addr read out mismatch				1 test run
	chip_rv_dm_lc_disabled	16320924222816358952759082696491852616992088799560198451894175610647906370076	226	UVM_INFO @ 3670.401180 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:738) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [] vs [*]) Major alert did not match expectation.				1 test run
	chip_sw_rv_core_ibex_lockstep_glitch	79486226636639663699912594804762742484754862711162490665672805474644804454116	327	UVM_INFO @ 2119.173420 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *				1 test run
	chip_sw_power_idle_load	77890333088105554292764464470365286059885723227265941877809088733403934076157	312	UVM_INFO @ 3535.806000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *				1 test run
	chip_sw_power_sleep_load	89921261117527540605833503870237083931239851920149328112848528032185357960017	318	UVM_INFO @ 3655.148000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *				1 test run
	chip_sw_ast_clk_rst_inputs	105697867970155916595021983245426581643931115302759737952559966599917818183092	327	UVM_INFO @ 10681.943885 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_.signed..scr.vmem could not be opened for r mode				1 test run
	rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	92980356000258841294047427944676660730772488745613116709621957965783150988691	325	UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_.signed..scr.vmem could not be opened for r mode				1 test run
	rom_e2e_sigverify_always_a_nothing_b_bad_dev	20228183289275741413131873650278530182101700329958221893627563671282005334776	327	UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '$stable(key_data_i)'				1 test run
	rom_keymgr_functest	56509732769779448226621340888759138324940391878592320613467816021231325038671	327	UVM_ERROR @ 5364.803400 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M UVM_INFO @ 5364.803400 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---