Simulation Results: clkmgr

 
07/05/2026 15:30:24 DVSim: v1.34.0 sha: 9bbcf3f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.49 %
  • code
  • 98.44 %
  • assert
  • 95.76 %
  • func
  • 86.28 %
  • line
  • 99.12 %
  • branch
  • 98.85 %
  • cond
  • 95.06 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
91.67%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.880s 17.152us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.830s 17.598us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 1.030s 16.572us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 3.380s 280.060us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.700s 211.414us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.460s 77.911us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 1.030s 16.572us 1 1 100.00
clkmgr_csr_aliasing 1.700s 211.414us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.760s 40.550us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.930s 43.057us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 1.010s 98.497us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.900s 43.491us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.880s 17.152us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 1.360s 224.574us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 6.390s 2326.379us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 1.360s 224.574us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 23.020s 4877.283us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.740s 23.129us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 2.510s 392.267us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 2.510s 392.267us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.830s 17.598us 1 1 100.00
clkmgr_csr_rw 1.030s 16.572us 1 1 100.00
clkmgr_csr_aliasing 1.700s 211.414us 1 1 100.00
clkmgr_same_csr_outstanding 0.830s 34.349us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.830s 17.598us 1 1 100.00
clkmgr_csr_rw 1.030s 16.572us 1 1 100.00
clkmgr_csr_aliasing 1.700s 211.414us 1 1 100.00
clkmgr_same_csr_outstanding 0.830s 34.349us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 0.840s 28.033us 0 1 0.00
clkmgr_tl_intg_err 1.390s 68.841us 1 1 100.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 2.160s 419.844us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 2.160s 419.844us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 2.160s 419.844us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 2.160s 419.844us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
clkmgr_shadow_reg_errors_with_csr_rw 1.560s 100.207us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 1.390s 68.841us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 1.360s 224.574us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 6.390s 2326.379us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 2.160s 419.844us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.910s 63.255us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.780s 51.066us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.890s 49.410us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.790s 26.032us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.840s 49.389us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 1.030s 16.572us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 0.840s 28.033us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 1.030s 16.572us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 1.030s 16.572us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 0.840s 28.033us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 2.010s 440.802us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 35.040s 3793.722us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [clkmgr_common_vseq] expect alert:fatal_fault to fire 1 test run
clkmgr_sec_cm 94566690469210971399024697475875891605472575027668237181126876596280741950024 102
UVM_INFO @ 28033014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---