Simulation Results: edn/edn0

 
07/05/2026 15:30:24 DVSim: v1.34.0 sha: 9bbcf3f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.80 %
  • code
  • 80.63 %
  • assert
  • 95.01 %
  • func
  • 81.75 %
  • line
  • 96.96 %
  • branch
  • 89.40 %
  • cond
  • 85.20 %
  • toggle
  • 81.05 %
  • FSM
  • 50.54 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.940s 37.197us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.880s 24.721us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.870s 22.550us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.240s 118.043us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.480s 450.167us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.990s 30.440us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.870s 22.550us 1 1 100.00
edn_csr_aliasing 1.480s 450.167us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.060s 29.199us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.060s 29.199us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.060s 29.199us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.000s 23.100us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.110s 88.764us 1 1 100.00
errs 1 1 100.00
edn_err 0.930s 26.698us 1 1 100.00
disable 2 2 100.00
edn_disable 0.840s 16.435us 1 1 100.00
edn_disable_auto_req_mode 1.020s 61.129us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.700s 309.269us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.720s 23.785us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.860s 19.761us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.560s 235.180us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.560s 235.180us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.880s 24.721us 1 1 100.00
edn_csr_rw 0.870s 22.550us 1 1 100.00
edn_csr_aliasing 1.480s 450.167us 1 1 100.00
edn_same_csr_outstanding 1.030s 37.640us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.880s 24.721us 1 1 100.00
edn_csr_rw 0.870s 22.550us 1 1 100.00
edn_csr_aliasing 1.480s 450.167us 1 1 100.00
edn_same_csr_outstanding 1.030s 37.640us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 6.510s 541.054us 1 1 100.00
edn_tl_intg_err 1.560s 58.196us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.790s 26.226us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.110s 88.764us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.510s 541.054us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.510s 541.054us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 6.510s 541.054us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 6.510s 541.054us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.110s 88.764us 1 1 100.00
edn_sec_cm 6.510s 541.054us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.110s 88.764us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.560s 58.196us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 55.560s 13062.476us 1 1 100.00